Abstract: A method for detecting defects during semiconductor device processing can include providing a substrate having a semiconductor comprising layer with electrically isolated application and test circuits are formed thereon, directing an electron current inducing beam to the test circuit; measuring a current between the first and the second contact pads in the test circuit; determining an electron beam induced current (EBIC); and identifying one or more defect locations in the test circuit based on the EBIC and a location of the electron beam corresponding to the EBIC. A test circuit can include a plurality of semiconductor devices connected in parallel, a first contact pad coupled to a first terminal of the semiconductor devices, and at least a second contact pad coupled to a substrate terminal associated with the semiconductor devices.

Abstract: There is provided a method of manufacturing a semiconductor device. In one aspect, the method includes providing a strained silicon layer having a crystal orientation located over a semiconductor substrate having a different crystal orientation. A mask is placed over a portion of the strained silicon layer to leave an exposed portion of the strained silicon layer. The exposed portion of the strained silicon layer is amorphized and re-crystallized to a crystal structure having an orientation the same as the semiconductor substrate.

Abstract: In one aspect, there is provided a method of manufacturing a semiconductor device. This method includes forming gate structures over a substrate, wherein the gate structures include gate electrodes located adjacent source/drain regions. A protective layer is formed over the gate structures and a CMP layer is formed over the protective layer. A portion of the CMP layer and the protective layer is removed to expose a portion of the gate electrodes with remaining portions of the CMP layer and the protective layer remaining over the source/drain regions. The exposed portions of the gate electrodes are doped with an n-type dopant or a p-type dopant, and the remaining portions of the CMP layer and the protective layer located over the source/drain regions are removed subsequent to the doping.

Abstract: The present application is directed a method for preparing a mask pattern database for proximity correction. The method comprises receiving data from a design database. Mask pattern data describing a first photomask pattern for forming first device features is generated. The first photomask pattern is to be corrected for proximity effects in a proximity correction process. A second set of data is accessed comprising information about second device features, wherein at least a portion of the second set of data is relevant to the proximity correction process. The second set of data is manipulated so as to improve the proximity correction process, as compared with the same proximity correction process in which the second set of data was included in the mask pattern database without being manipulated. At least a portion of the mask pattern data and at least a portion of the manipulated second set of data is included in the mask pattern database.

Abstract: A method for fabricating a semiconductor device includes forming a silicided gate utilizing a CMP stack. The CMP stack includes a first liner formed over the underlying semiconductor device and a first dielectric layer formed over the first liner layer. The first dielectric layer is formed to approximately the height of the gate. A second liner layer is formed over the first dielectric layer. Since the first dielectric layer is formed to approximately the height of the gate, the second liner over the moat regions is at approximately the height of the first liner over the gate. A CMP process is performed to expose the first liner over the top of the gate. Since the first dielectric layer is formed to the height of the gate, a portion of the second liner remains over the moat regions after the CMP process. Afterwards, the gate is exposed and a silicidation is performed to create a silicided gate.

Abstract: Areas of a semiconductor substrate where semiconductor devices are not to be formed are filled in with dummy active areas. Whole dummy active areas are formed in areas of the semiconductor substrate where semiconductor devices are not to be formed, and partial dummy active areas are formed in areas of the semiconductor substrate where semiconductor devices are not to be formed, but where whole dummy active areas can not be accommodated. The dummy active areas are staggered so as to provide uniform parasitic capacitive coupling to overlying leads regardless of the placement of the leads. The dummy active areas are substantially evenly separated from one another by dividers. The dummy active areas and dividers are formed concurrently with formation of semiconductor devices in non-dummy active areas. The dummy active areas mitigate yield loss by, among other things, providing more uniformity across the substrate, at least with regard to parasitic capacitances and stress and subsequent processing.

Abstract: A method of fabricating an integrated circuit (IC) including at least one drain extended MOS (DEMOS) transistor and ICs therefrom includes providing a substrate having a semiconductor surface, the semiconductor surface including at least a first surface region that provides a first dopant type. A patterned masking layer is formed on the first surface region, wherein at least one aperture in the masking layer is defined. The first surface region is etched to form at least one trench region corresponding to a position of the aperture. A dopant of a first dopant type is implanted to raise a concentration of the first dopant type in a first dopant type drift region located below the trench region. After the implanting, the trench region is filled with a dielectric fill material. A body region is then formed having a second dopant type in a portion of the first surface region. A gate dielectric is then formed over a surface of the body region and the first surface region.

Abstract: Provide is a method of making a mask layout, an integrated circuit device made by a method, a computer readable medium, and a mask for forming contact holes. The method can comprise patterning a first feature along a first axis, determining a first set of areas adjacent to the first feature, wherein each of the areas in the first set of areas is within a first angle away from the first axis, and wherein each of the areas in the first set of areas is within a first distance away from the first feature, and patterning a second feature in at least one of the first set of areas so as to form a mask layout, wherein each of the first feature and the second feature are one of a virtual feature and a real feature.

Abstract: An ESD protection circuit (710) is guarded by a parallel first precharge elimination circuit (720) relative to an I/O pad (721) and a parallel second precharge elimination circuit (730) relative to a VDD pad (731). The precharge elimination circuits are synchronized with the ESD protection circuit to eliminate any precharge voltage to ground before an ESD pulse affects the I/O pad or VDD pad. A diode (722) is connected between I/O pad and VDD. Circuit (720) is between I/O pad and ground (740) and is powered by the same VDD. Circuit (720) includes a first resistor (723), a first nMOS transistor (724), and a first RC timer including a second resistor (725) and a first capacitor (726). Circuit (730) includes a third resistor (733), a second nMOS transistor (734), and a second RC timer including a fourth resistor (735) and a second capacitor (736).

Abstract: The object of the invention is to provide a semiconductor device that can form photodiodes that do not short circuit, without damage that causes leakage, despite formation of the opening part, and its manufacturing method. The second semiconductor layer (12, 16) of the second conductivity type is formed on the main surface of the first semiconductor layer (10, 11) of the first conductivity type. Element-separating regions (13, 14, 15, 17) formed at least on the second semiconductor layer separate the device into the regions of plural photodiodes (PD1-PD4). Conductive layer 18 is formed on the second semiconductor layer 16 in a pattern that is divided for each of the photodiodes and is connected to the second semiconductor layer 16 along the outer periphery with respect to all of the plural photodiodes. Insulation layer (19, 21) is formed on the entire surface to cover conductive layer 18.

Abstract: A method of measuring temperature across wafers during semiconductor processing includes the step of providing a correlation between a peak wafer temperature during a processing step and a change in wafer surface charge or surface potential following the processing step. A first wafer to be characterized for its peak temperature spatial distribution during the processing step is processed through the processing step. The wafer surface charge or surface potential at a plurality of locations on the first wafer are measured following the processing step. A peak temperature spatial distribution for the first wafer is then determined based on the correlation and the wafer surface charge or surface potential measured in the measuring step.

Abstract: A method of fabricating an interconnect structure, comprising exposing an empty deposition chamber to a process that includes generating reactive species produced from a source gas in the presence of a plasma. The method further comprises terminating the plasma and then introducing a semiconductor substrate with a metal layer thereon into the chamber while the reactive species are present in the chamber.

Abstract: The disclosure herein pertains to fashioning a low noise junction field effect transistor (JFET) where transistor gate materials are utilized in forming and electrically isolating active areas of a the JFET. More particularly, active regions are self aligned with patterned gate electrode material and sidewall spacers which facilitate desirably locating the active regions in a semiconductor substrate. This mitigates the need for additional materials in the substrate to isolate the active regions from one another, where such additional materials can introduce noise into the JFET. This also allows a layer of gate dielectric material to remain over the surface of the substrate, where the layer of gate dielectric material provides a substantially uniform interface at the surface of the substrate that facilitates uninhibited current flow between the active regions, and thus promotes desired device operation.

Abstract: The present invention provides circuitry for writing to and reading from an SRAM cell core, an SRAM cell, and an SRAM device. In one aspect, the circuitry includes a write circuit coupled to the SRAM cell core that includes a write transistor gated by a write word line. The circuitry also includes a read buffer circuit coupled to the SRAM cell core to read the cell without disturbing the state of the cell. The read buffer circuit includes a read transistor gated by a read word line, the read transistor coupled between a read bit-line and a read driver transistor that is further coupled to a voltage source Vss. The read driver transistor and a first driver transistor of the cell core are both gated by one output of the cell core. The read transistor has an electrical characteristic that differs from that of the core cell first driver transistor.

Abstract: The present invention provides an integrated circuit and a method of manufacture therefore therefor. The integrated circuit (100, 1000), in one embodiment without limitation, includes a dielectric layer (120, 1020) located over a wafer substrate (110, 1010), and a semiconductor substrate (130, 1030) located over the dielectric layer (120, 1020), the semiconductor substrate (130, 1030) having one or more transistor devices (140, 1040) located therein or thereon. The integrated circuit (100, 1000) may further include an interconnect (170, 1810) extending entirely through the semiconductor substrate (130, 1030) and the dielectric layer (120, 1020), thereby electrically contacting the wafer substrate (110, 1010).

Abstract: A method of forming an interconnect structure for an integrated circuit, including the steps of providing a substrate and forming a dielectric stack on the substrate including an etch-stop layer, a low-k dielectric layer, and a hardmask layer. The method further includes the steps of patterning a photoresist masking layer on the dielectric stack to define a plurality of feature defining regions and plasma processing the substrate in a plasma-based reactor, The processing step includes etching a plurality of features into the hardmask layer and at least a portion of the low-k dielectric layer and performing a plasma treatment process in situ in the plasma-based reactor, where the plasma treatment process includes flowing at least one hydrocarbon into the reactor and generating a plasma, where a mass flow rate of the hydrocarbon is at least 0.1 sccm. The method also includes forming a metal conductor in the plurality of features.

Abstract: According to various embodiments, two-print two-etch methods and devices are disclosed that can be used to form features, such as ghost features, on a substrate. The disclosed methods can be incorporated into, for example, altPSM, attPSM, and binary lithographic method for making semiconductor devices. a method of forming a semiconductor device is provided. The exemplary methods can include defining a plurality of first features and at least one ghost feature on a photosensitive layer by exposing a first mask to a light, wherein the first mask comprises a plurality of phase shift areas that change a phase of the light. A portion of a layer disposed under the photosensitive layer can be removed by etching to form the plurality of first features and the at least one ghost feature. One or more structures not requiring phase shifting can then be defined on the photosensitive layer by exposing a second mask to the light, wherein the second mask removes the at least one ghost feature.

Abstract: A high voltage field effect transistor device is fabricated. A substrate is provided. Isolation structures and well regions are formed therein. Drain well regions are formed within the well regions. An n-type channel stop resist mask is formed. N-type channel stop regions and n-type surface channel regions are formed. A p-type channel stop resist mask is formed. P-type channel stop regions and p-type surface channel regions are then formed. A dielectric layer is formed over the surface channel regions. Source regions are formed within the well regions. Drain regions are formed within the drain well regions. Back gate regions are formed within the well regions. Top gates are formed on the dielectric layer overlying the surface channel regions.

Abstract: The present invention provides a method for manufacturing an integrated circuit. In one embodiment, the method includes etching one or more openings within a substrate using an etch tool, and subjecting the one or more openings to a post-etch clean, wherein a delay time exists between removing the substrate from the etch tool and the subjecting the one or more opening to the post-etch clean. This method may further include exposing the substrate having been subjected to the post-etch clean to a rinsing agent, wherein a resistivity of the rinsing agent is selected based upon the delay time.

Abstract: One aspect of the invention provides a method of forming a semiconductor device (100). One aspect includes forming transistors (120, 125) on a semiconductor substrate (105), forming a first interlevel dielectric layer (165) over the transistors (120, 125), and forming metal interconnects (170, 175) within the first interlevel dielectric layer (165). A carbon-containing gas is used to form a silicon carbon nitride (SiCN) layer (180) over the metal interconnects (170, 175) and the first interlevel dielectric layer (165) within a deposition tool. An adhesion layer (185) is formed on the SiCN layer (180), within the deposition tool, by discontinuing a flow of the carbon-containing gas within the deposition chamber. A second interlevel dielectric layer (190) is formed over the adhesion layer (185).