Abstract: A method and apparatus for accessing a color palette in a color graphics system synchronously and asynchronously. Address and data registers coupled to the color palette are operated synchronously in a pipeline fashion using clock pulses having a pixel scanning rate when the palette is used for refreshing a color monitor. The address and data registers are operated asynchronously, i.e. rendered transparent to addresses and data, respectively, when the palette is updated by a CPU.

Abstract: An array-word-organized memory system comprising a plurality of columns and rows of memory chips, an address bus routed through all of the memory chips, a plurality of selectable CAS lines wherein one of the CAS lines is routed through each one of said plurality of columns of memory chips and a plurality of selectable RAS lines wherein one of the RAS lines is routed through each one of said plurality of rows of memory chips. In operation, selected X and Y addresses are applied to the memory chips together with the strobing of selected ones of the CAS and RAS lines during four sequential time periods for addressing arbitrary arrays of pixels stored in the memory chips.

Abstract: An arithmetic logic circuit comprising a plurality of cells of conventional logic circuits for performing logical and arithmetic operations in combination with a kill circuit in each one of the cells which is responsive to bits of first and second operands T and B, a clock signal .0.1*, a propagate bit P and a carry-in bit C.sub.in for selectively providing a carry-out bit C.sub.out and/or a carry-bypass circuit coupled to each one of a plurality of sets of cells which is responsive to propagate bits P from said cells in each set, a clock signal .0.2* and a carry-in bit C.sub.in for allowing said carry-in bit C.sub.in to bypass selected ones of the cells.

Abstract: A memory comprising apparatus for selecting redundant rows of memory cells wherein the addressing of a defective regular row of memory cells coupled to a first set of bit lines results in the selection of a redundant row of memory cells coupled to a second set of bit lines such that signal interference resulting from the simultaneous enablement of two word lines in the memory is avoided.

Abstract: An ECL circuit comprising an output transistor having a base, a resistor coupled to the base, a first circuit responsive to a deselect signal OE for drawing a first current through the resistor and a second circuit responsive to the deselect signal OE for drawing a second current through the resistor, said first and said second currents combining in said resistor for providing a predetermined turn-off bias potential on said base of said output transistor. The predetermined turn-off bias potential reduces the emitter current of the output transistor such that the noise immunity of a data bus is preserved when a plurality of output transistors are coupled in parallel to the data bus.

Abstract: A single-chip fixed/floating-point arithmetic processor, a three port ALU, a plurality of storage registers R, S, F0 and F1, a constant store circuit and an output data register F. Two of the storage registers R and S are provided for storing 64-bit input operands and two of the regusters F0 and F1 are provided for storing 64-bit results of operations performed in the ALU. Each of the registers are provided with three output ports and corresponding pass gates for selectively transferring data from the registers to the three inputs of the ALU under the control of control signals applied to the pass gates. The constant store is also coupled to one of the input ports of the ALU by a pass gate for transferring constants to the ALU under the control of a pass gate. Results of the ALU are provided to the data output register F for further processing off-chip.

Abstract: An ECL circuit comprising an output transistor having a high output voltage VOH guard band and a low output voltage VOL guard band with a temperature compensating network coupled to the output transistor for causing the high level output voltage VOH and low level output voltage VOL of the output transistor to remain within the maximum and minimum limits of the VOH and VOL guard bands over a wide temperature range.

Abstract: An apparatus is described for summing the products of a predetermined number of successive pairs of numbers. In the apparatus there is provided an arithmetic unit having a first and a second input and an output, a first, a second and a third register and a first and a second multiplexer. In operation, a first pair of numbers are multiplied and the product thereof stored in the third register. Thereafter, a second pair of numbers are multiplied and the product thereof stored in the second register. Thereafter, the contents of the second and third register are added and the sum thereof stored in the third register. After the sum of the products of the first and second pairs of numbers are stored in the third register, the products of succeeding pairs of numbers are stored in the second register.

Abstract: A memory comprising a plurality of memory cells, a column decoder, a row decoder, a plurality of shift registers and a multiplexer is provided for addressing the memory cells in a conventional manner or in a high-speed sequential mode. In the sequential mode alternate cells from each of two sets of cells are addressed and their contents provided on a data output line, or data presented to them on a data input line, at a system clock rate which is much faster than the conventional mode.

Abstract: A method and apparatus for transferring data between a disk and a CPU is disclosed comprising a pair of toggling header buffers and a pair of toggling data buffers. In operation, data is transferred between a sector on a disk and one of the data buffers under the control of one of the header buffers. While the data in the header buffer is being transferred between the data buffer and a CPU, data is transferred between an adjacent sector on the disk and the other data buffer under the control of the other header buffer. The rate of transfer of data between the data buffer and the CPU is higher than the rate of transfer of the data between the disk and the other data buffer. This provides sufficient time to check the data transferred from and to the CPU for errors and to address a new sector on the disk prior to the completion of the data transfer of the previous sector between the disk and the data buffer.

Abstract: A method and apparatus for generating a check sum and a syndrome for detecting errors in a series of bytes comprising a plurality of stages, each stage comprising a plurality of networks of exclusive OR gates, a memory and an exclusive OR gate for exclusively ORing the outputs of the networks resulting from a byte transmitted therethrough with the results stored in a memory in a previous stage due to a previous byte. Each of the stages and the networks therein correspond to a term in a Reed-Solomon polynomial. Except for differences in the number and construction of the networks in each stage, each of the stages are substantially identical and can be selectively used for detecting single and double burst errors.

Abstract: A method and apparatus for transferring data in parallel from a smaller to a larger register is described, in which the larger register comprises a first and a second set of master and slave latches with a one shot employed for clocking the master latches in the first set. In operation, a first word from the smaller register is latched into the first set of master latches in response to an output from the one shot which occurs on the trailing edge of a clock pulse applied to the larger register. On the leading edge of a subsequent clock pulse applied to the larger register, a second data word is latched in the second set of master latches. Immediately thereafter the first and the second set of slave latches are opened for transferring the first and second words at their inputs to their outputs in parallel. Following the transfer of the first and second words to the outputs of the first and second set of slave latches, the slave latches close, latching the first and second words.

Abstract: A method and apparatus for reading data from a disk having missing or unreadable field address marks. Expected address marks are searched for within a time window which is generated using a counter. When an expected address mark is generated at any time within the time window, the counter is set or reset to generate another time window within which the next address mark is expected to occur. By starting or restarting the counter each time an expected address mark is detected the effects of variations in spindle speed which occur prior to the detection of the address mark are eliminated, thus increasing the probability that readable address marks will be detected within a time window.

Abstract: An output voltage driver apparatus for an ECL circuit driving a capacitive load is disclosed which comprises an emitter follower means having an output emitter and a reference emitter. The output emitter is connected to the capacitive load. A pull-down transistor means is connected to the output emitter and provides a transient pull-down current for a capacitive load when the output voltage swings from a high level to a low level. A biasing means is connected between the reference emitter of the emitter follower means and the pull-down transistor means so that the pull-down transistor means is biased to turn on when the voltage at the output emitter is higher than the voltage at the reference emitter by a turn-on voltage.

Abstract: An ECL circuit with a bias circuit is provided which tracks the gain and operating characteristics of other transistors in an integrated circuit. The bias circuit employs the bandgap reference voltage, V.sub.CS, as the power source. By a transistor and resistor network a bias circuit voltage is generated. The bias circuit is useful in providing a bias to the base of a dynamically switchable low drop current source useful in ECL circuits.

Abstract: A dynamic ECL circuit is provided which drives loads having significant capacitance. The dynamic ECL circuit may utilize single level or multiple level logic and may be configured, for example, as an OR/NOR gate. A capacitor is placed between the base of a current source transistor and a circuit point having a logic level complementary to the output connected to the current source. As logic transitions occur within the circuit and are presented on the output, a transient current will be experienced through the capacitor due to the shift in the complementary level thereby momentarily altering the voltage on the base of the current source transistor. The dynamic alteration of base voltage produces a momentary change in the current through the current source transistor which serves to both speed up the high-to-low transition time and the low-to-high transition time on the output line.

Abstract: An apparatus for calibrating a photoplethysmograph system comprising a white card mounted in the cone of a speaker. The card is mounted a predetermined distance from a photoplethysmograph sensor for providing an output from the sensor corresponding to the DC or venous mode. An oscillation is provided for oscillating the white card at a frequency corresponding to the average heartbeat for producing on the output of the sensor a signal corresponding to an average heartbeat. By adjusting the gain of the photoplethysmograph apparatus to obtain a constant amplitude output from the system, a calibration signal is obtained.

Abstract: An FM demodulating apparatus with a comparator. The comparator is responsive to a threshold signal and an input signal for providing an output signal which changes polarity each time the difference between the threshold signal and the input signal exceeds a predetermined magnitude. A circuit responsive to the input signal exceeding the threshold signal within a predetermined time period provides an output for controlling the magnitude of the threshold signal.

Abstract: A recirculating strip processing apparatus is described comprising a recirculating stripper chain, a recirculating tool chain, a recirculating carrier follower chain and a recirculating die chain in a removable cassette for continuous processing of integrated circuit packages and leadframes. The processes described include deflashing an integrated circuit package, removal of the dam bar from the leadframe and cutting and bending the leads of the individual integrated circuit packages. When repair or replacement is required, the cassette involved is simply removed from the apparatus and replaced by another cassette thereby minimizing "down time" of the apparatus.

Abstract: A method of removing bulk impurities from a semiconductor wafer is described comprising the steps of lapping the front and back surfaces of the wafer to remove 35 to 40 microns of material therefrom and to make the surfaces parallel, heating the wafer at a predetermined temperature preferably equal to or above the highest temperature to be used in subsequent device fabrication, etching the front and back surfaces of the wafer to remove 35 to 40 microns of material therefrom and thereafter polishing the front surface of the wafer for removing 20 microns of material therefrom. By means of the above process the number of surface defects caused by strain producing centers in the crystal lattice of the wafer is reduced from 500,000 defects per square centimeter to less than 1,000 defects per square centimeter.