Abstract: A computer design system is used to map a logical hierarchy corresponding to the logical functions of an electronic system into a physical hierarchy corresponding to the physical positioning of the actual electronic components which will implement the logical functions of the system. The logical hierarchy contains several levels of logical entities connected by signals, and the physical hierarchy contains physical packages corresponding to electronic components, such as integrated circuits. The mapping is accomplished by designating partition group assertions (PGAs) for each of the logical entities in the logical hierarchy. Each PGA corresponds to one of the physical packages in the physical hierarchy. Each entity is grouped by common PGA designation, and each signal of each entity is classified as external, if the signal connects entities located on different physical packages, or internal, if the signal connects entities located on the same physical package.

Abstract: A device control unit operating under the protocol of a parallel bus is connected by a serial link to a channel that is primarily adapted to operate under a different protocol with device control units connected by a serial link. An extender unit interconnects the parallel bus and the serial link and performs the specific operations of the parallel bus protocol. The channel and the extender unit send serial frames on the link for data transfer and associated operations. These frames are constructed according to a protocol that provides an intermediate step in translating between the protocol of the serial control units and the protocol of the parallel control units. The channel is operable in either mode (by microcode) and the new protocol permits the serial channel mode to be independent of the protocol of the parallel control unit and it permits the two modes to be closely similar in many features.