Abstract: A method for the characterization of large scale wafer topography is applied to improving yields in the manufacture large scale integrated (LSI) devices. First, the heights at the center, the edge and an intermediate point are measured on eight equally spaced radii. This provides eight values each for Y.sub.s and Y.sub.e which are averaged. Then the shape angle .alpha. is computed using the following equation: ##EQU1## The shape magnitude M is also computed using the following equation: ##EQU2## The thus computed values of .alpha. and M are correlated with individual wafer characteristics as to device performance and yield. Based on these results, the wafer processing is controlled to provide optimal wafer yield and isolation characteristics.

Abstract: A centrifuge vessel (10) for performing automated immunoassays is disclosed. The centrifuge vessel (10) comprises a center tube (11) and an outer waste chamber (15). A biomaterial (18) is held within the center tube (11) and is capable of binding specific analytes in test samples. In operation, the centrifuge vessel (10) is rotated at high speed about its longitudinal axis, thereby causing all fluid within the center tube (11) to be transported into the outer waste chamber (15) while the analyte of interest remains bound to the biomaterial (18) positioned within the center tube (11).

Abstract: A digital PLL circuit capable of stabilizing a phase comparison operation to largely reduce a jitter of an output signal, including a peak detection circuit for detecting a peak of an input signal level, a two-points sampling circuit for sampling two data points determined at a predetermined time interval in the peak to output two sample values, an inclination calculation circuit for calculating an inclination value from the two sample values, and a discrimination circuit for discriminating whether the inclination value is zero or either a positive or negative value to output a control signal for a VCO depending on the discrimination result.

Abstract: An apparatus for polishing edge chamfers of a semiconductor wafer to mirror gloss, having a rotatory cylindrical buff formed with annular groove(s) in its side and a wafer vacuum holder capable of holding and turning the wafer circumferentially, wherein the cylindrical buff is adapted to shift axially, and the annular groove has a width substantially greater than the thickness of the wafer, and a drive mechanism for axially biasing the cylindrical buff is provided.

Abstract: An automatic cleaning apparatus cleans wafers one at a time without the necessity for transporting the wafers in a carrier such as a wafer cassette or basket. After a manufacturing step such as a polishing step, the wafers are carried to a loader assembly in a horizontal orientation under the influence of flowing liquid. The wafers are then individually erected into a vertical orientation by being first stopped by stopper pins which stand vertically on a wafer receiving plate of a suction arm including a suction nozzle which firmly holds the wafers while the arm is pivotally rotated until the wafer is positioned into a vertical orientation. The vertical orientation thus achieved allows the wafer to be gripped by a wafer gripping portion of a transportation robot including grooved gripping arms operated by a mechanism which limits the force applied to the wafer.

Abstract: A set of three-dimensional structures and devices may be wired together to perform a wide variety of circuit functions such as SRAMs, DRAMs, ROMs and PLAs. Both N-Channel and P-Channel transistors can be made. The P-channel devices are fabricated conventionally in separate N-wells or, alternatively, they are constructed in a like manner to the array N-channel devices. N and P diffused wire can be electrically joined at polysilicon contacts.

Abstract: Two or more rising pulse waves having different rates of voltage increase are applied to a measuring end of a cable and reflected waves from a fault point on the cable are detected to measure a turnaround propagation time between the measuring end and the fault point. Additionally, ratios of the rates of voltage increase of one pulse wave and the other pulse waves are calculated. A discharge delay time at the fault point is calculated from time differences of the measured turnaround propagation time and the ratios of the voltage increasing speeds and the discharge delay time is subtracted from the measured turnaround propagation time to calculate a real turnaround propagation time.

Abstract: An automated immunoassay analyzer includes a computer controlled instrument (10) and display (16). The display (16) provides a real-time presentation of all operations being performed within the instrument (10). A large number of samples can be loaded into the instrument (10), and the order of testing the samples can be rearranged according to a priority determined by the operator at any time. A wide variety of immunoassays can be performed on each sample and several different immunoassays can be performed on any one sample. Information related to the type of immunoassays being performed on particular samples is collected by a bar code reader (44) and this information is conveyed to the computer (12) for presentation on the display (16). The computer (12) tracks the progress of each immunoassay through the reaction circuit to the detection station (46).

Abstract: A rounding operation circuit for arithmetic logic unit of a signal processor provided for counting fractions over 1/2 as one and disregarding the rest for the positive and negative number, which comprises a decoder circuit having an (n+1)-long input to which a first input signal represented by two's complement and a second n-bit long input signal for specifying the rounded position of the first signal are entered, when the first input signal is positive, a signal in which the bit at the rounded position is "1" and the rest is "0" is emitted based on the second input signal and, when the first input signal is negative, a signal in which the bits less significant than the bit at the rounded position are all "1" and the rest is "0" is emitted; arithmetic logic unit for adding the output signal of this decoder circuit and the first input signal; and a rounding circuit for counting 1 and cutting away 0 positively and negatively symmetrically to any rounding position, to allow a fast and accurate rounding operation

Abstract: A device incorporated in a bidirectional CATV system for reducing noise introduced in an up-going channel at a subscriber station. A terminal unit and a protector perform monodirectional or bidirectional switching operations on the basis of a DC current which the terminal station selectively outputs.

Abstract: A method of holding utilizing a fixture with five discrete vacuum elements provides support at four peripheral points on a substrate and at the substrate center. Two peripheral vacuum elements are fixed in position on a rigid frame. The remaining peripheral elements and the center element are fixed to a gimbal disc. This gimbal disc is mounted on the frame in such a way that it has three degrees of rotational movement relative to the frame. Downward pressure of a substrate resting on the two fixed elements, brings all three gimbal disc mounted supports into contact with the substrate, without allowing or causing deflection of the substrate. The mounting is locked, and vacuum is applied to all the elements to secure the substrate in place for the planarizing operation.

Abstract: A test pattern including an aperture image and a line image including a plurality of parallel lines, forming a measurement graticule, overlapping the aperture image, permits determination of dimensions for correction of alignment of image centerlines by inspection rather than complex measurement with stationary optical instruments. Since the line pattern preferably includes a plurality of parallel lines of predetermined width and separated by a predetermined spacing, the line image can be made to overlie the aperture image without obscuring features of the aperture image which are significant to determination of the alignment correction dimension.

Abstract: A dosimeter with reproducible changes in .epsilon.', .epsilon.'', or their equivalent two parameter circuit representations, under a given treatment regime that correlate directly with changes in physical attributes of a material or fluid, such as strength, modulus or viscosity, is used to monitor the deterioration of the physical attributes of the material or fluid.

Abstract: A waveguide structure is directly extruded onto a surface from a nozzle placed a predetermined distance above the surface and which is moved relative to the surface, preferably by means of a translation table. The predetermined distance is preferably maintained constant and the speed of relative motion regulated to achieve a uniform degree of molecular orientation within the extruded material, thus maintaining a sufficiently uniform refractive index along the axis of the waveguide. Partitions within the nozzle allow the formation of a layered waveguide or the simultaneous formation of concentric cladding or protective layers. The waveguides are advantageously formed as a curtain which is later patterned, by direct writing on the surface or between chips mounted on an electronic module.

Abstract: A programmable antifuse element comprising adjacent bodies of germanium and aluminum or aluminum alloy form forming a low resistance connection of good mechanical and thermal properties when heated to a temperature where alloying of the aluminum and germanium occurs. Heating for the purpose of programming the antifuse element can be done by electrical resistance heating in the germanium, which may be doped to achieve a desired resistance value, or by laser irradiation. Due to the high resistance of intrinsic or lightly doped germanium, a resistance change ratio of greater than 10,000:1 is achieved.

Abstract: A switchable voltage generator is provided on-chip together with circuitry including transistors formed in accordance with several different technologies and optimized for operation at different voltages. Provision of a voltage generator on the chip avoids the need for dedicated connections for the lower voltage or voltages. To provide similar levels of burn-in voltage to the different transistor types, a bypass or shunt is provided across the regulator of the voltage generator. The on-chip voltage generator avoids the requirement for a large number of chip or module power connections for each supply voltage required in order to meet current requirements of different portions of chip circuitry. The use of a mode select receiver also avoids the requirement of additional connections to the chip. The combination of one or more switchable voltage generators with a mode select receiver allows economical and efficient electrically stressed testing of the chip at different levels of manufacture.

Abstract: An improved method of using an ID saw slicing machine for slicing a single crystal ingot in a direction normal to the axis of the ingot to obtain wafers, of which the improvement lies in that the cutting load which the blade of the ID saw slicing machine imposes upon the single crystal ingot is continually detected in terms of three vector elements along three mutually perpendicular directions throughout the slicing operation, and that, when the magnitude of that vector element of the cutting load which extends in the slicing direction exceeds a predetermined value, the feed rate of the ingot to the blade is decreased and, at the same time, the rotational speed of the blade is increased in accordance with a predetermined control pattern.

Abstract: A non-constrained total joint prosthetic replacement device for metatarso-phalangeal joint. A first component comprises a convex-bearing surface and a rearwardly projecting stem configured to be received in the resected metatarsal bony shaft, and a second component includes a concave-bearing surface and a stem configured to be received within the resected phalangeal bony shaft. A non-bearing intermediate land offsets the convex-bearing surface of the first component from the stem, allowing a full range of anatomical motion notwithstanding the presence of bony overgrowth.

Abstract: An error correcting code (ECC) function and a parity interface scheme providing a translation capability between the ECC and parity protocols is implemented for memory systems in personal computers (PCs). The ECC function addresses the problems of interfacing memory with a variety of other components that may communicate in words composed of differing numbers of bytes. A partial write function within an ECC module permits a read/modify/write operation without extra components, at faster speeds and with minimal use of the system bus. An improved parity/ECC protocol interface is implemented by choosing an appropriate ECC code to facilitate parity generation and checking. This is done by selecting a code that contains groupings of data bits corresponding to the desired parity scheme. The ECC XOR trees are modified to allow parity checking and error correction decode simultaneously, thereby eliminating the need for two sets of XOR trees in the interface.

Abstract: Two movable die members that are situated opposed to each other in an extrusion die assembly, the axis of movement of the two die members is parallel to the longer sides of the rectangular cross-section of a throat opening of the extrusion die assembly. The members move in a reciprocating back and forward movement to impart shearing forces to the surface of the extruded material with a resultant multiaxial orientation of the molecules or fibrils.