Abstract: A method and apparatus for preventing generation of third generation data of an original data recorded on a read-only region of a partial read-only memory (ROM) optical disk includes an operation for copying source data from the partial read-only memory to a read-write medium by first attempting to write check data on a read-write region of the partial ROM optical disk. If the check data cannot be written, the copy operation terminates. If the check data can be written, the source data is overwritten. Then, the source data is copied from the partial ROM optical disk to the read-write medium.

Abstract: A method and apparatus for processing sheets, includes placing a sheet on a carrier to form a sheet/carrier structure, sizing the sheet/carrier structure, stacking the sheet/carrier structure in a stacking apparatus having a second sheet stacked in advance therein, so that the sheet contacts the second sheet, aligning the sheets with pins, tacking the sheet to the second sheet and removing the carrier.

Abstract: To make a memory system smaller, a memory system includes a plurality of memory cell arrays including a plurality of pairs of bit lines, a plurality of first data amplifiers for amplifying data of corresponding pairs of bit lines, a reference voltage circuit for outputting a reference voltage level, and a plurality of second amplifiers for receiving an output of the corresponding first data amplifier and the reference voltage level, for judging which voltage level is higher between the output of the corresponding first data amplifier and the reference voltage level, and for amplifying the voltage level being higher.

Abstract: Deformation of a lifting ring of bimetallic structure or memory metal is matched to a solder softening or melting temperature to apply forces to lift a chip from a supporting structure, such as a substrate or multi-chip module, only when the solder connections between the chip and the supporting structure are softened or melted. The temperature of the chip, module and solder connections there between is achieved in a commercially available box oven or belt furnace or the like and results in much reduced internal chip temperatures and thermal gradients within the chip as compared to known hot chip removal processes. Tensile and/or shear forces at solder connections and chip and substrate contacts are much reduced in comparison with known cold chip removal processes. Accordingly, the process is repeatable at will without significant damage to or alteration of electrical characteristics of the chip or substrate.

Abstract: A cleaner hose includes a synthetic resin pipe and four reinforcing hard steel wires disposed spirally, at predetermined intervals, in the synthetic resin pipe wall. The reinforcing hard steel wires are coated wires which are coated with synthetic resin. The pipe wall includes inner and outer layers in which an under wound tape and an upper wound tape are spirally wound while being displaced by half pitch from each other.

Abstract: A bone stabilizing apparatus includes a stem member and an extension member, the stem member having a distal end for insertion within the intramedullary canal of a human humerus and the proximal end connected to the extension member. The extension member has radially directed threaded holes either pre-formed or created after the bone stabilizing apparatus is installed into the humerus. The threaded holes allow fixation of stabilizing screws with suture posts, or a washer structure to grip the surface of the bone and/or surrounding ligaments or muscle. A prosthetic or the natural humeral head can be attached to the extension member. In a preferred embodiment a guide structure directs the drill and stabilizing screws radially through the central axis of the extension member.

Abstract: A computer network, having at least three nodes for implementing predetermined functions, comprises an OBJECT PASSING AGENT (OPA) storing the access authorizations of the individual nodes relative to each other. By means of calls (passing, returned), the stored access authorizations may be modified. With the aid of a further call (inquire), access authorizations may be verified. The desired access authorizations are defined by the user in the interface descriptions of the individual nodes. These descriptions are used by a compiler to generate the previously mentioned calls for modifying or verifying access authorizations. To permit a node to access the function of another node, an access authorization to that effect (passing) is stored in OPA. Prior to implementation, each access is verified (inquire). Upon completion of the access, the access authorization in OPA is erased (returned). These calls are handled automatically, ensuring that node access operations are readily implemented.

Abstract: After forming a groove on one surface of a single-crystalline silicon layer, a silicon oxide layer is formed. Also, a polycrystalline silicon layer is formed on the silicon oxide layer to cover the groove. Subsequently, by a buffer layer of polycrystalline silicon is deposited over the polycrystalline silicon layer to form a smooth surface. Thereafter, a silicon oxide layer is formed on a separately prepared supporting substrate. After laminating both substrates by mating the buffer layer and the silicon oxide layer, annealing is performed. By this, voids which might otherwise be generated at the junction interface in the dielectric isolation substrate can be eliminated.

Abstract: A Verilog simulation method significantly reduces scenario execution time of very large scale integrated (VLSI) logic models that contain high numbers of sequential devices. A computer implemented method saves the state of sequential devices into a file at a chosen point in a simulation scenario and then inputs this file to initialize another simulation scenario. The method has the ability to utilize the user defined primitive (UDP) model data for the sequential devices present in the technology library. However, using the standard data structure available in the programming language interface (PLI), it is not possible to uniquely identify individual UDPs. UDPs have the characteristic of having only one output each. Therefore, it is possible to uniquely identify each UDP by the net name which is connected to this output. An exception to this is the situation where two or more like-named UDP outputs are connected to the same net.

Abstract: Modifications of a digital logic device, such as a static or dynamic random access memory (SRAM or DRAM) or pass gate logic circuit or the like, implemented with complementary metal-oxide-semiconductor (CMOS) structures formed with silicon-on-insulator (SOI or, more specifically, SOICMOS) technology effectively suppress transient parasitic bipolar current disturbances (e.g. transient half select write disturb instabilities) caused by a discharge current through a parasitic lateral bipolar transistor formed under the transfer gate field effect transistors. Level shifting of the "off" voltage applied to the gate electrode of the transfer gate transistor dynamically changes the gain of the cell transfer gate to increase memory cell stability without compromising the memory capacity per chip or read/write memory cycle time even though level shifting can greatly increase majority carrier density in the floating body (gate) of a SOICMOS transistor at a particular level shifted voltage range.

Abstract: A multi-byte per cycle string matching apparatus for compression of text files compares an input stream, at least two bytes per cycle, against cells of a history buffer and detects all match state trajectories indicative of a string, generates a corresponding signal, prioritizes among multiple concurrent strings and outputs a string termination signal based on that priority.

Abstract: A light receiving structure for waveguide type optical devices, which excels in productivity, is compactly formed and permits highly efficient coupling, is provided. A recess is provided in part of the surface of a substrate on which an optical waveguide is formed, and a light-receiving element is mounted on the recess, with its light-receiving face upward. Near the recess is formed an end face of the optical waveguide in advance, so that a light be emitted therefrom. On the other hand, over the substrate is arranged a cover in which a groove is formed in a position opposite to the optical waveguide and a reflector is formed in a position opposite to the light-receiving element. The light emitted from the optical waveguide is reflected by the reflector and coupled to the light receiving element.

Abstract: Large capacitance, low-impedance decoupling capacitors in SOI and their method of fabrication. A high conductivity trench substrate contact is made adjacent to the capacitor by removal of insulator lining the capacitor by use of an extra mask thereby making a substrate contact when the trench is filled with doped polysilicon. The inventive process is compatible with and easily integrated into existing SOI logic technologies. The SOI decoupling capacitors are formed in trenches which pass through the silicon and buried oxide layers and into the underlying silicon substrate.

Abstract: Methods and kits for detecting the presence of and quantifying the concentration of viable microorganisms in a liquid sample are provided. Enzymes present in viable microorgansims reduce an indicator reagent to produce a visible color change. No titrations or dilutions of the sample are necessary. Variations of the test are described which can be used to detect a threshold level of viable microorganisms, to detect the presence or absence of viable microorganisms and to quantify the concentration of viable microorganisms in a liquid sample. The results are obtained rapidly with those for the detection available within thirty minutes and those for the quantification available within thirteen hours.

Abstract: There is provided a photoresist including (a) a resin composed of a polymer having a compound represented with the following general formula ?1! within a structural unit thereof, and (b) a photo acid generator. ##STR1## wherein R.sup.1 represents a hydrogen atom, R.sup.2 represents a divalent hydrocarbon group including a bridged cyclic hydrocarbon group and having a carbon number in the range of 7 to 13 both inclusive, R.sup.3 and R.sup.4 represent a hydrocarbon group having a carbon number of 1 or 2, and R.sup.5 represents one of (a) a hydrocarbon group having a carbon number of 1 to 12, (b) a hydrocarbon group having a carbon number of 1 to 12 and replaced with an alkoxy group having a carbon number of 1 to 12, and (c) a hydrocarbon group having a carbon number of 1 to 12 and replaced with an acyl group having a carbon number of 1 to 13. The above mentioned photoresist produces no extra polymer by side reaction.

Abstract: Producing a gap between a source and/or drain region of a silicon-on-insulator (SOI) field effect transistor which is less than the thickness of a depletion region normally surrounding the source and/or drain region, preferably at zero volts bias, permits gain of a parasitic bipolar transistor formed therewith to be transiently reduced and the effective base-emitter junction capacitance to be transiently increased during only modes of operation in which the parasitic bipolar conduction dominates normal operation of the field effect transistor. Such transient reduction of gain coupled with a transient reduction of high frequency response reduces the parasitic bipolar current spike to a degree greater than previously achievable and is fully compatible with other techniques of reducing such current spike.

Abstract: In a microcomputer, a high-order address bus of a control processing unit (CPU) is coupled to a first input of an address selector and an address latch having an output coupled to a second input of the address selector. An output of the address selector is connected to one input of a multiplexer having the other input connected to a high-order data bus of the CPU and an output connected to high-order address/data bus terminals. In the case that the microcomputer is coupled to only 8-bit external memories, the high-order address is outputted through the high-order address/data bus terminals during a period of accessing the external memory, and the address latch and the address selector are controlled to output the high-order address latched in the address latch through the high-order address/data bus terminals during a period of executing no access to the external memory.

Abstract: A CRT touch screen having raster-generated light patterns at the viewing screen borders of a conventional CRT. Reflective surfaces proximal to the screen borders reflect the light patterns across the CRT surface to external photodetectors. Modulating the horizontal blanking signal or employing periodic non-reflective patterns on the reflective surfaces effects raster-generated light patterns having a unique time frequency higher than the vertical synch frequency, but lower than the horizontal synch frequency. A screen pointer blocks the lights patterns reflecting across the screen to two or more of the photodetectors. The blocking is time-relative to the CRT's horizontal and vertical synch signals. The photodetector outputs are bandpass filtered at the unique pattern frequency to suppress electromagnetic interference from the CRT's horizontal raster synch, the CRT's vertical synch and other electromagnetic and optical sources.

Abstract: A transaction manager intercepts all requests for service from any of a plurality of clients, establishes connections independently of task requests and assigns available servers to the requests in the order the requests are received in order to provide equitable distribution of service resources over an increased number of client/server connections. Preferably, the transaction manager provides for starting at least one server independently of any request, direction of all client requests for server connections to a transaction manager independently of any server, placement of task requests in a queue and starting and stopping additional servers based on queue length.