Patents Represented by Attorney, Agent or Law Firm Whitham, Curtis & Whitham
  • Patent number: 6144224
    Abstract: A new clock distribution network design for VLSI circuits which effectively reduces skew without the area and power penalty associated with prior clock designs. Two wires emanating from the clock in opposite directions or, alternatively, two wires connected in series and running parallel, are used to route clock signals from the clock source to the next routing segment. The next routing segment routes clock signals to the tapping point near the circuit component by two emanated wires from the previous routing segment. Clock signals from the routing segments are fed through two-input NOR gates (alternatively, two-input NAND gates) to the clock pins. The clock signal arrival time is roughly equal to the simultaneous switching gate delay plus the average arrival times from the two paths, which turns out approximately the same across different tapping points, thus minimizing clock skews. Narrow wires may be used for routing, resulting in moderate power consumption.
    Type: Grant
    Filed: July 6, 1999
    Date of Patent: November 7, 2000
    Assignee: International Business Machines Corporation
    Inventors: Jin-Fuw Lee, Daniel Lawrence Ostapko
  • Patent number: 6138150
    Abstract: A personal computer or workstation running a Web browser point and click interface is used to display and send information for remotely controlling a computer such as a mainframe. In the preferred embodiment, a web site or "home-page" is constructed on a secure HTTP (hyper text transfer protocol) server which comprises a Hardware Management Console (HMC). A user logs on to the Internet World Wide Web in a conventional manner by entering the address or uniform resource locator (URL) to connect to the secure HTTP server. Upon entry of a correct password the Hardware Management Console (HMC) home-page will be displayed. Icons representing various mainframe computer components are displayed which link to additional pages which the user can click on to monitor and control the mainframe computer. The color of the icons provide a summary of the status its representative component (e.g.
    Type: Grant
    Filed: September 3, 1997
    Date of Patent: October 24, 2000
    Assignee: International Business Machines Corporation
    Inventors: Stephen R. Nichols, Kurt N. Schroeder, Samuel L. Wentz
  • Patent number: 6136669
    Abstract: A semi conductor manufacturing process including uniform negative polarity wafer charging to remove or immobilize alkali ions such that the device becomes immune to their presence. The wafer is charged with a corona discharge at a 1MV/cm-2MV/cm bias field and low temperature (200.degree. C.-300.degree. C.) heating to bring mobile ions to the wafer's surface. Surface mobile ions are removed with a deionized (DI) water rinse or a standard sequential wafer wet cleaning step, immobilized with a normal gate (polysilicon) or metal contact formation step or both, thereby effectively removing mobile ions from the semiconductor structure.
    Type: Grant
    Filed: July 21, 1998
    Date of Patent: October 24, 2000
    Assignee: International Business Machines Corporation
    Inventors: Frederick Albert Flitsch, Min-Su Fung
  • Patent number: 6137042
    Abstract: A visual display is provide for music associated with a theremin or, in general, any space-controlled electric instrument. The theremin is a space-controlled electric instrument that produces an output of sound corresponding to the motion of the user, without being touched by the user. The device establishes a correspondence between motion and electric signals, then between such signals and either light and sound, or just light.
    Type: Grant
    Filed: May 7, 1998
    Date of Patent: October 24, 2000
    Assignee: International Business Machines Corporation
    Inventors: Jerome M. Kurtzberg, John Stephen Lew
  • Patent number: 6137129
    Abstract: A pair of directly coupled Field Effect transistors (FETs), a latch of directly coupled FETS, a Static Random Access Memory (SRAM) cell including a latch of directly coupled FETs and the process of forming the directly coupled FET structure, latch and SRAM cell. The vertical FETs, which may be both PFETs, NFETs or one of each, are epi-grown NPN or PNP stacks separated by a gate oxide, SiO.sub.2. Each device's gate is the source or drain of the other device of the pair. The preferred embodiment latch includes two such pairs of directly coupled vertical FETs connected together to form cross coupled invertors. A pass gate layer is bonded to one surface of a layer of preferred embodiment latches to form an array of preferred embodiment SRAM cells. The SRAM cell may include one or two pass gates. The preferred embodiment SRAM process has three major steps. First, preferred embodiment latches are formed in an oxide layer on a silicon wafer.
    Type: Grant
    Filed: January 5, 1998
    Date of Patent: October 24, 2000
    Assignee: International Business Machines Corporation
    Inventors: Claude L. Bertin, John E. Cronin, Erik L. Hedberg, Jack A. Mandelman
  • Patent number: 6136686
    Abstract: Provision of differential etching of layers by, for example, an etch stop layer or implantation, allows a second trough etch to be performed in accordance with a block-out mask (which does not require high accuracy of registration) to provide troughs or recesses of different depths in layers of insulator. When the recesses or troughs are filled by metal deposition and patterned by planarization in accordance with damascene processing, structurally robust conductors of differing thicknesses may be achieved and optimized to enhance noise immunity and/or signal propagation speed in different functional regions of an integrated circuit such as the so-called array and support portions of a dynamic random access memory.
    Type: Grant
    Filed: July 18, 1997
    Date of Patent: October 24, 2000
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Mark Jaso, Hing Wong
  • Patent number: 6137158
    Abstract: Parallel optical coupling apparatus for coupling a connector attached to one end of a parallel optical cable to a receiver or transmitter array. A parallel fiber optic assembly includes a receiver or transmitter array subassembly that houses a parallel optical coupler for transferring optical signals from an array of sources (e.g., lasers) in the assembly to the connector, or from the connector to an array of receiving elements in the assembly. A connector shell is provided that properly aligns the connector with respect to the optical coupler array.
    Type: Grant
    Filed: June 1, 1998
    Date of Patent: October 24, 2000
    Assignee: International Business Machines Corporation
    Inventors: Mitchell Simmons Cohen, Marco Gauvin, Glen Walden Johnson, Daniel M. Kuchta, Andre Lacerte, Nicholas Anthony Lee, Sylvain Ouimet, Stephen Louis Spanoudis, Stephane Tremblay, Jeannine Madelyn Trewhella
  • Patent number: 6134774
    Abstract: A coaxial cable connector includes a housing made from an electrically conductive material and a hollow, cylindrical sleeve extending from a first end of the housing. The sleeve is constructed from a material which is deformable onto a coaxial cable. An inner conductor connector projects from the first end of the housing at a point centrally positioned within the hollow, cylindrical sleeve. Insulation is positioned between the housing and the inner conductor connector from the housing, and an outer conductor connector projects from the first end of the housing at a point positioned with the hollow, cylindrical sleeve between the inner conductor connector and the hollow, cylindrical sleeve.
    Type: Grant
    Filed: February 25, 1997
    Date of Patent: October 24, 2000
    Inventors: Deborah Williams, Forest Williams
  • Patent number: 6133749
    Abstract: A programmable variable impedance output driver circuit uses analog biases to match driver output impedance to load input impedance. A current mirror is used to obtain a measurement of an external resistance value for matching the impedance of a driven load. The mirrored current generates the voltage "NBIAS" when passed through the resistively connected NFET. Similarly, the current is again mirrored and passed through a resistively connected PFET resulting in the voltage "PBIAS". The analog bias voltages, NBIAS and PBIAS are used to vary the impedance of complementary FETs in an impedance matched driver for a high degree of dI/dt control. The driver provides a high degree of flexibility because its turn-on and turn-off characteristics do not depend on a combination of digital control signals connected directly to the driving FETs as in the prior art.
    Type: Grant
    Filed: January 4, 1999
    Date of Patent: October 17, 2000
    Assignee: International Business Machines Corporation
    Inventors: Patrick R. Hansen, Harold Pilo
  • Patent number: 6134182
    Abstract: A comparator and variable delay circuit are provided to maintain the tracking between data and echo clocks in a double data rate (DDR)RAM device. This is accomplished by providing a global data signal (dummy data signal) that tracks with the actual memory array data. This global data signal is compared to the timing of the RAM clock (CLOCK) to determine a delay time between the two by which the pipeline clocks (CLKRISE/CLKFALL) must be delayed. As a result, the pipeline clocks are pushed out as needed so that they always transition after the array data arrives at the output latch. Therefore, as cycle time decreases, both echo clocks and data are pushed out identically and maintain their required tracking.
    Type: Grant
    Filed: October 19, 1999
    Date of Patent: October 17, 2000
    Assignee: International Business Machines Corporation
    Inventors: Harold Pilo, James J. Covino
  • Patent number: 6132226
    Abstract: A structure for mounting a semiconductor device or similar electronic part to a printed circuit board and a method therefor are disclosed. Electrodes are formed on the front of the circuit board while electrodes are formed on the electronic part. The circuit board and electronic part are affixed to each other by adhesive while holding thin metallic wires between their electrodes.
    Type: Grant
    Filed: November 12, 1998
    Date of Patent: October 17, 2000
    Assignee: NEC Corporation
    Inventor: Yuji Noda
  • Patent number: 6133948
    Abstract: An automated identification system comprises a first classification station which uses two laser sources and video imaging techniques to identify and distinguish between similar items such as, for example wooden cabinet doors and drawer fronts. Each laser produces a fan-shaped plane of light, perpendicular to the other, on front face of the door. The fan shaped planes of light produce a first profile stripe in the horizontal direction across the width of the door face and a second profile stripe in the vertical or length direction. A first video camera captures the image of the profile stripe across the width of the door. A second camera is used to capture the profile stripe in the vertical direction to determine whether the panel shape is square or cathedral shaped. A feature-based approach is used to process the captured profile stripes and compare them to a library of known profiles. A third camera, placed substantially parallel to the first camera captures the width measurement of the door.
    Type: Grant
    Filed: December 3, 1996
    Date of Patent: October 17, 2000
    Assignee: Virginia Tech Intellectual Properties, Inc.
    Inventors: A. Lynn Abbott, Bin Yuan
  • Patent number: 6129743
    Abstract: An apparatus and method for defibrillation utilizes a ratio of short and long window moving averages to provide optimum selection of the time for shock delivery.
    Type: Grant
    Filed: March 23, 1999
    Date of Patent: October 10, 2000
    Assignee: Virginia Commonwealth University
    Inventors: Peng-Wie Hsia, Rose Province, Eric Fain
  • Patent number: 6128752
    Abstract: A mechanism for handling processing errors in a computer system. The mechanism includes a first means for processing a stream of instructions, second means for detecting an error caused by a timing dependant defect and occurring during processing of the instruction by the first means and third means for varying the instruction processing cycle time of the first means in response to the detection of the error by the second means, and for causing the second means to retry at least a portion of the instruction subsequent to the varying. In a preferred embodiment, the mechanism uses the variable frequency oscillator, controlled by recovery code, to increase the system clock cycle time by a specified time (Textend) following what has been determined to be a critical fail and after normal retry has been unsuccessful. The increased cycle time extends the net slack and, thereby, provides tolerance to certain AC (path delay) defects which have developed in any cycle time dependant latch to latch segment.
    Type: Grant
    Filed: November 14, 1994
    Date of Patent: October 3, 2000
    Assignee: International Business Machines Corporation
    Inventors: Kevin Roy Griess, Ann Caroline Merenda, Donald Lloyd Pierce
  • Patent number: 6128510
    Abstract: A cordless modem comprises a radio pair interfaced to a standard data/fax modem which allows a user of a personal computer to wirelessly connect to a telephone line. One end of the radio pair is a remote unit interfaced to the modem contained within the PC while the other end is a base unit connected to a standard telephone wall jack. The base unit can selectively discriminate and adjust for signals received from a telephone voice handset or data signals received from the cordless modem remote unit. Upon receiving an off-hook signal or an incoming call signal, the base unit identifies the type of data (i.e., voice or computer modem data) and adapts accordingly by placing an FM modulator in either of a narrow band deviation or a wide band deviation covering the required range of the particular signal combined with local echo. That is, when voice data is present, a low deviation, narrow filter combination is selected.
    Type: Grant
    Filed: May 13, 1997
    Date of Patent: October 3, 2000
    Assignee: International Business Machines Corporation
    Inventors: Troy James Beukema, Michael Frank Cina, Ephraim Bemis Flint, Brian Paul Gaucher, Young Hoon Kwark, Modest Michael Oprysko, William Edward Pence, Saila Ponnapalli
  • Patent number: 6124199
    Abstract: A DRAM memory cell array includes a wiring layer formed at a storage-capacitor level of the cell for establishing a flipped connection of complementary bit lines, or for connecting support circuits in a DRAM cell array. The wiring layer includes a lower capacitor electrode and upper capacitor electrode which are formed simultaneously with respective plates of a storage capacitor. Both capacitor electrodes may be used to form distinct interconnections within a DRAM cell array.
    Type: Grant
    Filed: April 28, 1999
    Date of Patent: September 26, 2000
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Gary B. Bronner, David E. Kotecki, Carl J. Radens
  • Patent number: 6123465
    Abstract: The optical module has a semiconductor light emitting device, a lens, a holder for the device and the lens, and a receptacle core onto which a ferule of a counter optical plug is to be fitted. When the optical plug is connected, the semiconductor light emitting device is optically coupled with an optical fiber in the ferule by the lens. A step portion which forms a circular opening with setting the optical axis as the center axis and which eliminates coupling undesired light is disposed at a position which is on an emission side of the lens with respect to a contacting position of the-holder and the lens. Preferably, the optical module satisfies the following expressions:0.9<.phi./(NA.times.L.sub.1)<1.3 and L.sub.2 <L.sub.1 /2where .phi. is a diameter of the circular opening, NA is a numerical aperture of the optical fiber, L.sub.1 is a distance between an opening end on the side of the lens and the optical fiber, and L.sub.
    Type: Grant
    Filed: March 20, 1997
    Date of Patent: September 26, 2000
    Assignee: Nippon Sheet Glass Company LTD
    Inventor: Hideki Hashizume
  • Patent number: 6122496
    Abstract: When the frequency band of an intermediate frequency (IF) signal input to a filter rises due to temperature variation, the center voltage corresponding to the IF signal also rises. As a result, a difference occurs between the center voltage and a preselected reference voltage. An output current produced by converting the difference is so output as to increase a control current, thereby shifting the frequency characteristic of the filter to the higher frequency side. When the frequency band of the IF signal falls due to temperature variation, the center voltage also falls. The resulting difference between the center voltage and the reference voltage is also transformed to an output current. This output current is so output as to reduce the control current with the result that the frequency characteristic of the filter is shifted to the lower frequency side.
    Type: Grant
    Filed: February 27, 1998
    Date of Patent: September 19, 2000
    Assignee: NEC Corporation
    Inventor: Kenji Yoshioka
  • Patent number: 6117891
    Abstract: The present invention relates to treatment of pain with a new class of analgesic compounds. More particularly, the present invention relates to a method for reducing pain of a patient involving administering to a patient an effective amount of an aryl substituted olefinic amine compound. In one aspect, the inventive method of reducing pain in a patient involves use of metanicotine compounds as the analgesic agent.
    Type: Grant
    Filed: February 25, 1999
    Date of Patent: September 12, 2000
    Assignee: Virginia Commonwealth University
    Inventors: Billy R. Martin, Mohamad I. Damaj
  • Patent number: 6118788
    Abstract: Fairness algorithms and access methods enable non-zero channel access for wireless communication systems operating in a random access channel environment. Fair access to a random access channel for each station in a wireless network is assured by each station calculating a priority or probability for accessing the channel based on logical connections among certain stations, based on other stations perception of the channel and based on each calculating station's own perception of the channel properties.
    Type: Grant
    Filed: October 15, 1997
    Date of Patent: September 12, 2000
    Assignee: International Business Machines Corporation
    Inventors: Parviz Kermani, Babak Rezvani, Mahmoud Naghshineh, Claus Michael Olsen, Timucin Ozugur