Abstract: A data processor which includes a central processing unit (CPU) coupled to an address bus for supplying an address to an external memory and a data bus for supplying data to the external memory and receiving data from the external memory, and a control logic for controlling data exchange between the CPU and the external memory with a predetermined unit amount of data processing of the central processing unit. The external memory includes first and second DRAMs and the CPU executes the data exchange with units of four words. Each DRAMs has a memory area divided into a number of sub-areas each have four continuous addresses, so that the sub-areas of the first DRAM and the sub-area of the second DRAM are alternately assigned in continuous addresses in one memory space formed of the first and second DRAMs. When an continuous addresses are supplied, a controller controls so that the first and second DRAMs are alternately accessed.

Abstract: In order to detect the format of asynchronously, serially transmitted character data using a command signal which includes a plurality of command character data, wherein the beginning of each of the command character data is identified by a start bit, and the character length of each of the character signals is L (a positive integer), the start bit is detected and a train of pulses generated to enable each of the character data to be sampled; the character signal is sampled and converted into a corresponding parallel signal; each of the parallel character signals outputted are ascertained; the number of character data received is counted and it is determined if a predetermined matching is achieved.

Abstract: A digital phase demodulator and digital phase demodulation method in delay detection form uses digital circuitry without a subtracter and with low power consumption. A phase measurement timing signal generator (11) outputs the phase measurement timing signal (103) produced by sampling a reception symbol cycle signal (101) by a reception signal (102) modulated to the logical level. A phase counter (31) outputs a synchronous clock signal (105) coinciding with a frequency of a reference clock (108) multiplied by n times the carrier frequency of the reception signal (102) so that the phase is synchronized with the phase measurement timing signal (103). The phase counter (14) counts the phase clock (105), and is reset by the phase measurement timing signal (103). The decoder (15) decodes a counted value (104) of the phase counter as a phase rotation quantity to the modulation data (107).

Abstract: Reaction products of organosilane compounds or polydiphenylsilazane compounds and a novolac resin having phenolic groups can be used as O.sub.2 RIE barrier materials in semiconductor etching processes. These materials have low O.sub.2 etch rates and can be spun on to form crack-free thick layers. Particular RIE barrier materials contemplated have the general formula: ##STR1## wherein A is a methyl or phenyl group.

Abstract: Alkali corrosion resistant coatings and ceramic foams having superfine open cell structure are created using sol-gel processes. The processes have particular application in creating calcium magnesium zirconium phosphate, CMZP, coatings and foams.

Abstract: Anhydrous ammonium fluoride is used as a safe source of hydrogen fluoride for etching native or other silicon dioxide layers from silicon substrates. Heating the anhydrous ammonium fluoride above its sublimation temperature results in the generation of hydrogen fluoride gas which etches the silicon dioxide. Controlled amounts of water vapor are used during the etch reaction to ensure complete etching of the thin oxide layers down to within hundredths of a monolayer and to achieve precise etch rate control.

Abstract: A curve generator has a group of registers, a group of files, an operator, a comparator and a sequencer. The curve generator interpolates for a curve in the vicinity of a plurality of designated control points, for example, a Bezier curve or a Spline curve, by calculating coordinate values of middle points between the control points on the basis of coordinate values of said control points. The curve generator realizes, an exclusive hardware, from an algorithm for generating the curve and, therefore, is capable of generating the curve at extremely high speed.

Abstract: Power supply for an EOT unit in which an electrical generator driven by air from the train air brake pipe provides the primary power to the EOT unit. The power supply of this invention may be incorporated as part of the EOT unit or it may be supplied as a power kit modification for existing EOT units in order to replace electric storage batteries in these units.

Abstract: A differential circuit comprises a differential stage responsive to input voltage levels in an ECL range for producing an output signal at an output node, a setting stage associated with the differential stage and responsive to a set signal in a CMOS range for setting the output node to a predetermined level, wherein a level-shift element is coupled between a bipolar transistor responsive to the set signal and the common emitter node of bipolar transistors responsive to the input voltage levels so that each bipolar transistor is prevented from destruction due to excess reverse bias voltage applied to the base node and the emitter node.

Abstract: Aluminum and aluminum alloys are protected from corrosion by immersion in an alkaline lithium or alkaline magnesium salt solution. Immersion in the salt solution causes the formation of a protective film on the surface of the aluminum or aluminum alloy which includes hydrotalcite compounds. A post film formation heat treatment significantly improves the corrosion resistance of the protective film.

Abstract: An image reversal process for self-aligned implants in which a mask opening and plug in the opening are used to enable one implant in the mask opening, another self-aligned implant in the region surrounding the opening, and a self-aligned electrode to be formed in the opening.

Abstract: A ghost cancelling circuit is provided with a gain limiting block for limiting recursive coefficients for a ghost cancelling filter to a level less than 0 dB in a frequency domain, so that the gains of the recursive coefficients are limited both in the frequency domain and in the time domain. Accordingly, the ghost cancelling filter will never oscillate.

Abstract: A semiconductor memory device having a plurality of (N) SRAMs (Static Random Access Memories). The device equally divides all of the data into N blocks and writes each of the N blocks of data in respective one the N SRAMs. In a read mode operation, the device reads different data from the N SRAMs at the same time. This is successful in reducing the chip area and current consumption.

Abstract: A digital multiplex communication system for carrying out digital multiplex communication between a plurality of terminal stations, at least two including one initiating party and the other party to communicate with, via a branching unit. In this system, groups of bits in a communication frame are allocated in advance for use in communication between one party and the other. In order to diagnose the state of the transmission line to the other party including the branching unit, loopback setting signals for setting the other party in the loopback test mode and loopback test signals are inserted into specific bit positions of the preallocated groups of bits in performing communication.

Abstract: A carrier module such as a chip carrier or a circuit board has a matrix of programmable connection pads for attaching a VHDLSI chip. Each pad is encircled by circuit elements (lines or vias) providing different power or signals and one of the lines or vias is selectively connected to the pad to program the connection. The pads have cut outs at the connection points to the vias and/or lines in order to simplify making of connections. The programming connections between the vias and/or lines and the pads are made after pre-finishing the board by depositing evaporated metal to form a bridge between each pad and a via or line selected for each pad. Then a passivation layer of polyimide is deposited on the vias and/or lines with an aperture at the center of each pads so that solder connections to attach the chip to the carrier module do not erroneously bridge to additional vias and/or lines.

Abstract: Requestors for a busy port in a multi-port communication system are enqueued in wait chains. The connectivity of a crossbar switch is employed to store the wait chains. Elements of the wait chain are modified to provide the right connections; that is, a group of ports are connected by what may be regarded as a form of linked list but where the pointers are comprised of connections in the switch itself. These connections are used both for storing the list structure as well as passing information.

Abstract: A pulse-width-modulated, quasi-resonant, d.c. to d.c. converter that has an auxiliary switch that periodically kills the resonance.

Abstract: Electrically conducting vias and lines are created by a three step process. First, a controlled amount of a soft, low resistivity metal (12) is deposited in a trench or hole to a point below the top surface of the dielectric (10) in which the trench or hole is formed. Subsequently, the low resistivity metal (12) is overcoated with a hard metal (16) such as CVD tungsten. Finally, chemical-mechanical polishing is used to planarize the structure. The hard metal (16) serves the function of protecting the low resistivity metal (12) from scratches and corrosion which would ordinarily be encountered if the low resistivity metal were subjected to the harsh chemical-mechanical polishing slurries. An ideal method for partially filling trenches or holes in a substrate is by sputtering at elevated temperatures such that metallization at the bottom of a trench or hole separates from metallization on a top surface adjacent the trench or hole.

Abstract: A corner test structure for multi-layer thin-film modules. In the corner of each layer a test structure is formed as part of the process for forming the layer itself. This corner test structure is designed to emulate the wiring pattern of the layer itself in terms of density and pattern. Each test site also includes vias for forming, in combination with vias from preceding and succeeding layers, via chain which emulate the via chains extending through the active wiring region of the module itself. Each test site structure includes a large array of test pads only a few of which are used at any given layer. The entire test pad array of each level is connected by vias to the test pattern on adjoining levels so that a test structure pattern at a given layer may be accessed from pads at each succeeding level and from pads on the upper surface of the completed module.

Abstract: A high-speed clock delay circuit in which an external differential digital clock signal is connected to a pair of differentially connected, current switching transistors. Emitter follower drivers couple the switching transistors to differential delayed clock output terminals. A pair of diodes cross-coupled between the differential output terminals and the switching transistors provide a relatively large Miller Effect capacitance, the charging and discharging of which provides a delay in the switching of the transistor pair, as measured differentially. Changing the charging and discharging current through the emitter follower driver, changes the bias across the diodes and thus changes their effective capacitance.