Abstract: Metal organic chemical vapor deposition (MOCVD) is used to form a layer of a metal oxide on the surfaces and within the pores of a porous ceramic material. The metal oxide is formed from one or more inexpensive metal organic precursors which permeate the pores of the substrate as a vapor. Surface reactions on the heated substrate convert the metal organic precursors to their metal oxide. The technique has particular utility in creating catalysts with very large surface areas and in providing a protective coating on ceramic materials that prevents or reduces damage from hostile environments. In a preferred embodiment, aluminum isopropoxide, [(CH.sub.3).sub.2 CHO].sub.3 Al, and titanium ethoxide, Ti(C.sub.2 H.sub.5 O).sub.4, are used simultaneously or successively as precursors to generate a Al.sub.2 TiO.sub.5 coating on a porous ceramic substrate such as SiC or porous refractory cement candle filters.

Abstract: Provision of a digital controller in which the controller controls the bearing coil current by means of a switching bridge that periodically reverses the applied voltage to the coil. The controller selects an applied voltage from a plurality of discrete voltage sources. When a rapid change in the load current is required, a relatively large magnitude of applied voltage is used. When a relatively constant magnitude of average load current is required, a relatively smaller value of voltage is applied.

Abstract: Reaction products of organosilane compounds and a novolac resin having phenolic groups have been found to have a very low rate of etching, thereby enabling the material to also be used as an RIE barrier in semiconductor manufacturing processes.

Abstract: A signal processing circuit includes an instruction memory for storing arithmetic instructions, a instruction decoder for decoding the instructions read from the instruction memory, an arithmetic circuit for carrying out arithmetic process in accordance with the instructions decoded by the instruction decoder, data memory for storing data to be processed by the arithmetic circuit, and a multi-port type register for storing data read from the data memory and the results of the arithmetic results. In the signal processing circuit, arithmetic processes in the arithmetic circuit are carried out in parallel by transferring data between the multi-port type register and the arithmetic circuit in accordance with one instruction.

Abstract: An electronically programmable read-only memory module has an embedded micro-controller for program/data updating.Upon power up, the module acts as a prior art ROM. The embedded micro-controller in a standby mode is responsive to data arriving from a download communication interface that is accessible by an external port on the module. The external port and download communication interface is independent of the system of which the module is an operating component. When a command is received from the download communication interface, the micro-controller switches the memory device to respond to micro-controller inputs that starts an update session. The micro-controller receives download data from the download communication interface and writes it into the memory device. When the download process terminates, the micro-controller switches the memory device back to its system interface.

Abstract: A circuit for discriminating whether or not a given point exists within a predetermined linear area, comprises first and second registers for storing first and second boundary values defining the predetermined linear area. A first detection circuit receives the first boundary value and a value of the given point, and a second detection circuit receives the second boundary value and the value of the given point. Each of the first and second detection circuits generating a first signal indicating that the boundary value is not greater than the value of the given point, a second signal indicating that the boundary value is equal to the value of the given point, and a third signal indicating that the boundary value is greater than the value of the given point.

Abstract: This shift amount detector determines the shift amount to normalize binary bit data. It is provided with means to add, to an n bit data to be normalized, at least one bit of logical value "0" on the side of the least significant bit. The data with additional logical value "0" has its bits reversed by the bit reversing circuit when the data is negative or positive. The data with the additional logical value "0" is input to the bit detecting circuit as it is or as data with reversed bits according to the selection by the selecting circuit. The bit detecting circuit detects the bit position where "1" or "0" appears for the first time by searching the bits one by one starting from the most significant bit and outputs the result of detection to the shift amount calculating circuit. The shift amount calculating circuit determines the shift amount based on the detected bit position.

Abstract: Memory cells in the semiconductor memory section are supplied with a current from an N-channel transistor which is one of the components forming a current-mirror circuit through a column selector and also supplied with a current from another current passage formed by N-channel transistors connected in series between a power supply source and the column selector. The N-channel transistor is turned on for a predetermined short period of time in response to an externally supplied pulse only at the start of accessing to the memory cell. Thus, a parasitic capacitor coupled to a column line is charged quickly through two different current passages, whereby the time for accessing read-only memory cells is effectively shortened.

Abstract: An integrated gate and semiconductor barrier layer diode which functions as a regular diode when the gate is turned off and as, a Schottky barrier diode with the gate turned on.

Abstract: This invention contemplates the provision of a noise immune integrated circuit receiver in which the voltage reference to one side of an emitter-coupled current switch moves in response to the input signal, in a direction opposite the input signal. This provides the gate with a threshold hysteresis, making it immune to noise without requiring a large swing in input signal.

Abstract: A method for conducting immunoassays in an automated fashion is disclosed. A biological fluid under test is placed in a tube (11) which has a solid support (18) therein to which a specific analyte in the biological fluid will be selectively bound. After the analyte in the biological fluid is bound to the solid support (18), the tube (11) is rotated at high speed about its longitudinal axis causing the biological fluid to be transported up the inside walls of tube (11), over the open terminal end (16), and into waste chamber (15). The solid support (18) with the bound analyte may easily be washed by flushing the inside of tube (11) with water or other suitable fluids and rotating the tube (11) at high speed about its longitudinal axis.

Abstract: A Viscoelastic medium with fibers dispersed throughout eliminates the need for a constraining layer, thus reducing the size and weight of a damping treatment.

Abstract: An error controller for use in a debugging microprocessor includes a bus error detection circuit for generating an exception request signal when an external bus error signal is supplied through an external input terminal and an exception control circuit responding to the exception request signal so as to control an exception processing. A double bus error detection circuit receives the external bus error signal for stopping an operation of a microprocessor when the external bus error signal is detected in the way of the exception processing. A bus error status saving circuit is provided for controlling the bus error detection circuit so as to save, when an interrupt request is given through a debug interrupt request terminal, a bus error status held in the bus error detection circuit indicating that the exception processing for the bus error is being executed when the interrupt request is given, so that the bus error detection circuit is brought into a condition of no bus error.

Abstract: A support for a roll of paper or similar material. The support comprises a shaft divided into two portions (10 and 11). The inner end of the portion (11) is internally threaded to receive an externally threaded boss (1) on the portion (10) The boss (14) carries a rubber ring (17) located between two washers (16 and 18). When the two portions (10 and 11) are assembled, the ring (17) is squeezed between the washers (16 and 18) so that its diameter expands until it grips the interior of the paper roll.

Abstract: An apparatus and method electronically registers or aligns ideal raster data to real raster data for subsequent processes such as inspection systems and image processing systems. The electronic image registration system receives ideal and real images in scrolling buffers wide enough to hold the width of the image and high enough to hold the difference in a skewed image. In other words, the real and ideal upper corners must be contained within the buffers for any possible kind of misalignment or distortion. Each buffer has a selector to randomly access frames of image in the vertical direction. Each buffer image frame is moved horizontally out of its lower swath and into its new position in the next upper swath. Horizontal movement of each buffer is independent, such that adjustable sequential access in the horizontal direction is available.

Abstract: Tantalum (or hafnium) oxide layers, alternated with silicon oxide layers in a dielectric stack reflector type mask for high power laser ablation, are wet etched at a high temperature with a highly caustic solution, preferably potassium hydroxide, to provide a much increased manufacturing yield in comparison with known processes such as ion milling. High feature density is achieved through the use of a resist which is built in two patterning steps. Preferably, a chromium layer is deposited and covered with an organic resist which is patterned by an optical or electron beam exposure. The chromium is then etched by means of the resist mask to form a resist for the caustic wet etch of the tantalum (or hafnium) oxide either separately or together with silicon oxide layers of the dielectric stack reflector mask to be used in the laser ablation process at high power.

Abstract: A portable particle detector assembly for detecting particle contamination in the reaction chamber of a plasma processing tool used in semiconductor manufacture. The detector is comprised of a scanner assembly for providing a scanned laser beam and a video camera placed opposite the scanner assembly for monitoring light scattered by particles within the volume of the reaction chamber.

Abstract: A semiconductor device where high voltage CMOS transistors and low voltage CMOS transistors are installed on a single chip, is manufactured by a silicon gate CMOS process. In order to reduce the number of repetitions of photolithographic process, low voltage N channel transistor domains and high voltage P channel transistor domains are simultaneously implanted by B ion, and low voltage P channel transistor domains and high voltage N channel transistor domains are simultaneously implanted by P ion.

Abstract: Aa single crystal pulling apparatus installed on a frame body further includes a second frame body which is founded independently from the main chamber to rigidly support the winder assembly, and a hermetical and flexible tube which is provided between the winder assembly and the pull chamber to prevent any stress and vibration from travelling from the winder assembly to the pull chamber and vice versa, while providing a communication passage between the winder assembly and the pull chamber.

Abstract: CMOSFETs control the power in a bipolar logic gate to regulate its operating speed and hence its delay. In a specific embodiment of the invention, an n-channel CMOSFET controls the constant current through an emitter-coupled current switch, comprised of a pair of bipolar integrated circuit transistors. A p-channel CMOSFET, in series with each collector of the switch pair, establishes the collector voltage so as to maintain constant the output swing of the gate as the power through the gate is varied in order to regulate the gate delay. An error signal, indicative of factors that can cause variations in gate delay and the inverse of the error signal are generated by an on-chip circuit. The error signal is coupled to the n-channel CMOSFET and the inverse of the error signal is coupled to the p-channel CMOSFET. Thus, as the switch current is decreased in order to increase the gate delay, the collector impedance is simultaneously increased so the collector voltage, and hence the gate swing, remains constant.