Abstract: A new integrated circuit for interfacing a standard IEEE 796 bus to a VSB-type buffer bus. This integrated circuit includes a DMA channel for high speed access of the IEEE 796 bus to the buffer bus, and a slave bus channel for high speed access of the buffer bus to the IEEE 796 bus. A third bus interface connects to a local processor to assist in arbitration and control during some types of data transfers.

Abstract: The subject invention is a circuit and method of providing the sum of first and second n bit binary numbers having a difference of one or less. The method comprises combining the least significant bits of the numbers in a first coincidence gate to provide the least significant bit of the sum, combining the nth and (n-1)st bits of the numbers in a first logic network to provide the most significant bit of the sum, and combining solely the ith and (i-1)st bits of the numbers in an ith logic network to provide the ith bit of the sum, for all values of i where 1<i<n+1.

Abstract: A circuit for regulating the output voltage of a switched mode power supply having a current mode magnetic amplifier includes a current transformer for sensing current flow through the magnetic amplifier. The sensed current is provided to a circuit which includes a resistor for developing a pulsating voltage and a storage capacitor for converting the pulsating voltage to a tracking voltage and storing the tracking voltage. The tracking voltage and a reference voltage are provided to a differential amplifier, the output of which operates a transistor which controls the operation of the magnetic amplifier, thereby regulating the output voltage of the power supply.

Abstract: The method comprises: selecting an examination window whose size covers the image data associated with a character within a set of characters; presenting image data for a known character to the examining window to obtain a probability density function (PDF) for each pixel within the examining window for each character in the set of characters to be found or segmented to generate a composite PDF for each pixel within the examining window; and using the composite PDF to determine when the examining window is positioned over image data associated with a character within the character set.

Abstract: The subject invention is a device for joining and separating first and second printed circuit boards connectable by a socket on one of the boards and a plurality of pins projecting from the other of the boards. The device comprises a screw held captive to the first board but rotatable therein, and a spacer fastened to the second board and having a threaded hole for receiving the screw. The pins are inserted into and withdrawn from the socket by the engagement and disengagement, respectively, of the threaded hole by the screw.

Abstract: An electronic module detachably mounted on a shopping cart includes a scanner for scanning bar coded information on items selected for purchase, a data processing device for data storage and control purposes and video recording apparatus capable of recording a view of the selected item as it is scanned and again as it is placed in a receptacle in the shopping cart to enable a customer to generate a record of items selected, which record can be used to facilitate checkout operations, and to provide security against improper scanning, or failure to scan, items selected for purchase.

Abstract: A method of measuring message response time performance of a data processing system includes the generation of timing messages when a data or status message is sent from a data terminal, such as a point of sale terminal in the system to a central processing unit, and when a data message is received at the terminal from the central processing unit. The timing messages include identification of type of message, time data taken from a timer in the terminal, and a sequence number which permits related messages to be paired so that the time values in each can be compared to determine a response time for the total period required for transmission of messages from the terminal to the central processing unit, any necessary data processing at the central processing unit and transmission of a message from the central processing unit back to the terminal.

Abstract: A circuit for the stable synchronization of an asynchronous data signal. The circuit comprises a first latch for receiving a first asynchronous data signal, a first delayed system clock signal, and a synchronized reset signal and for providing a system clock synchronized version of the first asynchronous data signal. A first delaying circuit receives a system clock signal and the first asynchronous data signal and provides the first delayed system clock signal. The circuit also includes a second latch for receiving a second asynchronous data signal which is a function of the inverse of the first asynchronous data signal and a second delayed system clock signal, and for providing the synchronized reset signal. A second delaying circuit receives the system clock signal and the first asynchronous data signal and provide the second delayed system clock signal.

Abstract: A printed circuit board assembly is disclosed which includes a number of rigid printed circuit boards connected by a number of flexible printed circuit panels. Integrated circuits and similar components are mounted on the rigid printed circuit boards. The components are interconnected by printed circuit conductors of the rigid printed circuit boards and the flexible printed circuit panels. The resulting board assembly can provide a manifold increase in the usable component area over a single flat, rigid printed circuit board when it is folded and installed into a standard cylindrical, coolant filled container.

Abstract: A switch mode power supply includes an AC to DC converter, a pulse width modulator for generating a series of pulses to control the switching of the DC across the primary winding of a transformer, and a start-up circuit connecting the AC to a power input of the pulse width modulator. A thermistor provides thermal protection for converter and start-up circuit components during abnormal operation, and a switch for disconnecting the start-up circuit and bypassing the thermistor after the power supply has been started improves power supply efficiency by eliminating power loss through the start-up circuit and thermistor.

Abstract: A CMOS gate isolated gate array configured with a single polysilicon layer and preferably two metallization layers, wherein the cell pitch is equal to the first and second metallization pitches by referencing the metallization layers, contacts and vias to a grid, and referencing the polysilicon layer to a half grid. Further refinements include the use of channel regions between parallel and adjacent chains of complementary transistors, wherein the width of the channel is equal to three times the pitch of the cell. In another form, a base set of the gate array includes diffused resistors in the channel regions suitable for matching discretionary interconnection.

Abstract: A data entry keyboard apparatus includes a key switch array (18) in a keyboard unit (12) connected via a cable (14) to a tamper-resistant module (28) which contains control circuitry (16). The control circuitry (16) includes a random pattern generator (30) which generates successive random patterns, causing the selection of a single column and a random pattern of rows, thereby effecting the simulation of key actuations. An EXCLUSIVE-OR gating network (56a-56d) is effective to distinguish a genuine key actuation from simulated key actuations. The invention prevents the ascertainment of actuated keys by unauthorized tapping connections applied to the keyboard unit (12) or the cable (14).

Abstract: A capacitor protection circuit for protecting bulk storage capacitors in a storage capacitor circuit in an electronic power supply. The capacitor protection circuit is operatively coupled to the storage capacitor circuit and comprises a first and second thyristor. The first and second thyristors are selected so that when the voltage across one of the storage capacitors in the storage capacitor circuit exceeds a predetermined voltage, the second thyristor will trigger the first thyristor to cause an excessive amount of current to be drawn through a fuse in the electronic power supply, thereby causing the fuse to blow and uncoupling the electronic circuit from an AC input. Another embodiment is disclosed to show how the capacitor protection circuit can be used in a 110 or 220 volt environment by utilizing a switch.

Abstract: A thermal transfer ribbon includes a substrate which has a thermal sensitive coating and a protective layer. The thermal sensitive coating is a solvent based wax mixture dispersed in a binder mix along with pigments. The protective layer is a water based mixture of ink, alcohol and carbon black which remains nonintegral with the thermal sensitive coating.

Abstract: A method and apparatus for displaying a high resolution image on a low resolution CRT with a minimal loss of information. Even rows of a source or matrix of binary pixels are stored in an "even" video RAM and odd rows are stored in an "odd" video RAM at addresses corresponding to the locations of the binary pixels within the matrix. In a preferred embodiment, a group of four pixels corresponding to a portion of the image is converted to a single gray value which is used to control the intensity of the beam control within the CRT.

Abstract: An integrataed circuit fabrication process for creating field oxide regions having substantially no bird's beak, a relatively planar concluding surface, substantially no stress induced dislocations at the edges of the active regions, and a substantial absence of notches or grooves at the edges of the active silicon, by a selective combination of material dimensions and process operations. In one form of practicing the invention, the process utilizes a relatively thick pad oxide below the masking nitride layer, and a second, very thin, sidewall masking nitride layer. The thin sidewall masking nitride layer does not utilize an underlying pad oxide layer. Upon oxidation, the thin sidewall nitride is concurrently lifted and converted to oxide, the materials and dimension being selected to ensure that when the field oxide level approaches the level of the thick pad oxide layer stresses at the corners of the active silicon region are relieved through various oxide paths and accentuated oxidation effects.

Abstract: A method and apparatus for minimizing rejections when using correction stickers on documents which are to be read by a single channel or "deep" MICR read head in subsequent reading operations. The method entails printing the correct MICR data on the correction sticker (which is placed over the incorrect MICR data) so that the correct MICR data is purposely off registration with the incorrect MICR data underneath the correction sticker so that the correct MICR data on the correction sticker will be encountered by a read head before the incorrect MICR data underneath the correction sticker is encountered. A double printing of the correct MICR data on the correction sticker also causes dynamic thresholding circuits associated with common MICR readers to "key in" on the high signal level on the MICR ink on the correction sticker and thereby render the incorrect MICR data signal underneath the correction sticker to the level of "noise".

Abstract: A multiplying digital to analog converter using ladder networks and binary weighted load compensation to allow integration and video frequency operation. In one form, the circuit is configured from field effect transistors which incorporate by virtue of their structural and operational characteristics both the switching and resistive functions of R-2R ladder networks. The circuit is used to convert digital format words representing intensity and color (red, green and blue) into analog red, green and blue display drive signals. According to that configuration, the output of the digital to analog intensity word converter serves as the reference for the three digital to analog color word converters. Loading effects attributable to differences in the bit content of the color words are offset by a binary weighted switched load which is responsive to a digital compensation word. The switched load is also connected to the output of the intensity word converter.

Abstract: An opening in a front panel of an automated teller machine (ATM) normally permits a portion of an internal mechanism to protrude therethrough to receive customer cards or for similar purposes. When the internal mechanism of the ATM is withdrawn for servicing, the protruding portion of the mechanism is withdrawn from the opening. A vertically slidable door is provided to close said opening whenever said protruding portion is withdrawn, in order to prevent access to the interior of the ATM by unauthorized persons. The door is operated by mechanism responsive to the movement of the internal mechanism.

Abstract: A computer memory prefetch architecture for accelerating the rate at which data can be accessed from memory and transmitted to a processor when successive addresses are numerically consecutive. Upon the identification of a consecutive address sequence, the succession of real addresses are generated directly by a counter. The memory of the computer system is partitioned into odd and even banks which are selectively addressed using the odd and even segments of the address generated in the counter. Output data from each memory bank is stored in a corresponding register operable to transmit the data entered therein during a previous memory address cycle while the anticipated next address data is written into the other register. The prefetch architecture may be meaningfully used to accelerate the access rate of a memory shared by multiple processors.