Abstract: A switched mode power supply has a high side switching transistor coupled between a voltage source and a load for generating the output voltage at the load. A driver circuit drives the high side switching transistor. A first resistor divider is coupled to the output voltage and has a first tap. An error amplifier has a first input coupled to the first tap and a compensated feedback loop. A second resistor divider is coupled to the output voltage and has a second tap, resistance of the second resistor divider being less than resistance of the first resistor divider. A switch is coupled to the second tap and to the first input of the error amplifier for connecting the second tap to the first input of the error amplifier when the output voltage of the switched mode power supply reaches a first predetermined voltage.

Abstract: A ground fault detection device includes a sense coil including a primary winding and a secondary winding to detect current in a line conductor and a neutral conductor. It also includes a capacitor in parallel with the secondary winding and a virtual inductor to form a resonance circuit having a signal proportional to the current and being indicative of a ground fault condition.

Abstract: A power supply circuit is proposed for supplying current to a pair of white LEDs connected in series. The circuit comprises a DC-DC power converter, with a charge pump coupled to the output of the DC-DC power converter. A super capacitor is coupled to the charge pump to be charged to a voltage on top of the converter output in a first mode of operation. The super capacitor is discharged through the pair of LEDs during a second mode of operation. A control stage is provided for switching between the first mode of operation and the second mode of operation.

Abstract: A semiconductor device includes a semiconductor substrate, a first p-channel laterally diffused metal oxide semiconductor (LDMOS) transistor formed over the semiconductor substrate and additional p-channel LDMOS transistors formed over the semiconductor substrate. First drain and gate electrodes are formed over the substrate and are coupled to the first LDMOS transistor. Additional drain and gate electrodes are formed over the substrate and are coupled to the second LDMOS transistor. A common source electrode for the first and second LDMOS transistors is also formed over the substrate.

Abstract: A device to accurately identify the wheel position where each tire has a radio wave transmitter installed without special means or operation during application by using a simple and compact configuration. This TPMS has sensor modules 14A, 14B, 14C, 14D on the transmission side equipped by tires 12FL, 12FR, 12RL, 12RR installed on automobile 10 and main device 16 on the receiving side loaded in automobile 10. Main device 16 is comprised of a group of two antennas 18, 20, receiver 22, and display 24. Two antennas 18, 20 are arranged appropriately to receive the radio waves transmitted by each of sensor modules 14A-14D with a phase difference between them.

Abstract: A delay applied to a turn-on time for a high side switch in a switch mode power converter prevents oscillation between continuous and discontinuous conduction modes under light load conditions. The delay equalizes turn-on time for a high side switch with respect to continuous and discontinuous modes, so that turn-on time is not treated differently between the different modes. The delay value can be set for be equivalent to a propagation delay through a driver for a low side switch, in addition to a turn-off time for the low side switch. The addition of the delay element tends to maintain the switch mode power converter in a discontinuous mode under light load conditions and avoids oscillation between discontinuous and continuous conduction modes.

Abstract: A linear voltage regulator is provided which has a pair of complementary power transistors connected “back to back” in series between a voltage input and a voltage output. A current sense circuit including a current sense resistor is connected in parallel across one of the power transistors, such as the one connected to the voltage input. As long as the voltage drop in the current sense circuit remains small, i.e. less than app. 0.7V, the current flowing through the bulk diode of the power transistor remains negligible and the entire output current flows through the current sense circuit. For higher output currents the voltage drop across the current sense circuit is limited by the parallel bulk diode of the power transistor. The current sense resistor can be dimensioned to generate a relatively high voltage drop of e.g. 100 mV, and a high accuracy of open load detection is achieved without the requirement for a high precision comparator.

Abstract: One embodiment of the invention includes a switching power supply system. The system includes a switch network comprising at least one switch configured to provide an output voltage based on switching activity thereof. The system also includes a switching controller configured to control the switch network to maintain the output voltage provided at an output based on a feedback signal associated with the output voltage. A converter pulse detector is configured to detect an output voltage overshoot condition based on the switching activity of the switch network corresponding to a transition in an output load to which the output voltage is provided.

Abstract: In a method and system for translating voltage levels to interface electronic devices, a voltage translator is operable to perform the translation of voltage levels of the bi-directional signals exchanged between the electronic devices in accordance with an open-drain mode of operation and in accordance with a push-pull mode of operation. The voltage translator includes edge-rate accelerators to detect signal transitions and includes configurable resistors to provide a direct current (DC) drive current and a DC bias to hold desired voltage levels. The voltage translator is operable in the open-drain mode to detect a presence of an electronic device, and is operable in the push-pull mode upon the detection of the electronic device.

Abstract: Embodiments of the present disclosure provide a fault protection circuit, a method of operating a fault protection circuit and a voltage regulator. In one embodiment, the fault protection circuit is for use with the voltage regulator and includes an output power section having first and second MOS transistors configured to provide a regulated voltage on an output node of the voltage regulator. The fault protection circuit also includes a gate pull-down section connected to the first and second MOS transistors and configured to provide a gate pull-down MOS transistor to limit a current through the first and second MOS transistors during a current overload fault condition on the output node.

Abstract: System and method for synchronizing the low speed mirror movement of a mirror display system with incoming frame or video signals, and synchronizing buffered lines of video data to the independently oscillating scanning mirror. According to one embodiment of the invention, the peak portions of the low speed cyclic drive signal are synchronized with the incoming frames of video by compressing or expanding the peak portion or turn around portion so that each video frame begins at the same location on the display screen. The actual position of the high frequency mirror is determined by sensors and a “trigger” signal is generated to distribute the signals for each scan line such that the scan lines are properly positioned on the display.

Abstract: Methods and apparatus for controlling a digital power supply are disclosed. An example method includes storing a first set of coefficients for controlling a digital power supply in a memory of the digital power supply, associating the first set of coefficients with a first set of characteristics of an input voltage for the digital power supply, storing a second set of coefficients for controlling the digital power supply in the memory of the digital power supply, associating the second set of coefficients with a second set of characteristics of the input voltage, receiving a first voltage from a voltage source at the digital power supply, determining that the first voltage has the first set of characteristics, and, in response to determining that the first voltage has the first set of characteristics, applying the first set of coefficients to the digital power supply.

Abstract: An RFID tag is provided, which has a transponder part with an antenna coil arranged in the transponder part. A mounting part is also provided for fixing the tag in a mounted position. The mounting part has an elongate portion that is engagable with the transponder part so as to be received in the transponder part when the tag is in the mounted position. Further, the tag comprises a magnetic material arranged in the elongate portion of the mounting part.

Abstract: A switched capacitor measurement circuit is provided for measuring the capacitance of an input capacitor with a parallel parasitic resistor. The circuit comprises a switching arrangement, a reference capacitor, a steered current sink and an operational amplifier with an output, a non-inverting input connected to a reference voltage source and an inverting input connected to a first terminal of the input capacitor. The current sink is steered to compensate for a charge current due to the parasitic resistor. Still further, the circuit comprises a digital adder and an analog-to-digital converter with an analog input connected to the output of the operational amplifier and a digital output connected to a first input of the digital adder.

Abstract: An electronic device includes an operational amplifier, with the operational amplifier having an amplifier input stage coupled with a first output node to an amplifier output stage. A compensation capacitance is connected between an output node of the amplifier output stage and the first output node of the amplifier input stage, thereby operating as a compensator for stabilizing the operational amplifier. The compensation capacitance provides a parasitic diode drawing a first leakage current from the first output node of the amplifier input stage, a leakage current compensation circuit being coupled to the first output node of the amplifier input stage and coupled to a second output node of the amplifier input stage for drawing a first current from the first output node and a second current from the second output node. The leakage current compensation circuit is adapted such that the second current is greater than the first current by an amount corresponding to the first leakage current.

Abstract: This invention provides a type of solid-state image pickup device characterized by the fact that for a solid-state image pickup device with a broad dynamic range, it is possible to suppress the dark current than photoelectrons overflowing from the photodiode, as well as its driving method. Plural pixels are integrated in an array configuration on a semiconductor substrate. Each pixel has the following parts: photodiode (CPD), transfer transistor (?T), floating diffusion (CFD), accumulating capacitive element (CS), accumulating transistor (?S), and a reset transistor. During the accumulating period of photoelectric charge, voltage (?) over that applied on the semiconductor substrate, or ?0.6 V or lower than the voltage applied on the semiconductor substrate, is applied as an OFF potential on the gate electrode of at least one transfer transistor, the accumulating transistor and the reset transistor.

Abstract: Methods and apparatus to control a digital power supply are disclosed. An example method includes calculating a duty cycle of a pulse width modulated signal to control an output of a digital power supply, initializing an output of a counter that forms a pulse width modulator to increment by a first increment up to a counter maximum value for a first period and to decrement by the first increment for a second period, dividing the duty cycle by a constant to determine a multiple of the duty cycle to apply to each power stage of the power supply, calculating a first threshold percent by subtracting the multiple of the duty cycle from one hundred percent, setting a first threshold to be the first threshold percent multiplied by the counter maximum value, and controlling the power factor controller based on the first threshold.

Abstract: A converter for a multi-phase current network can include a plurality of current sensors, each of the plurality of current sensors being configured to detect current for a respective phase of the multi-phase network. A current averaging circuit is configured to provide an indication of the average current for the multi-phase network based on the current detected by each of the plurality of current sensors. A modulator is configured to modulate at least one phase of the multi-phase network independently of each other phase of the multi-phase network based on a difference between the current detected for the at least one phase and the average current for the multi-phase network.

Abstract: A method of and system for modulating buck and boost modulation ramps of a multiple switch node power converter without overlap. As the pulse width or duty cycle of the signal to a modulated complementary switching pair approaches a pre-established reference pulse width or duty cycle, plural fixed-width or fixed duty cycle pulses are generated and introduced to a nonmodulated complementary switching pair. A controller detects proximity to the pulse width or duty cycle limit and, correspondingly, initiates prematurely a pseudo-buck-boost mode in the power converter by generating fixed-width or fixed duty cycle pulses to the nonmodulated complementary switching pair while the duty cycles or pulse widths to the modulated complementary switching pair are still controlled by the appropriate modulation ramp. The net effect is that the power converter reaches its optimal operating point without overlap and eliminates any sub-harmonic switching.

Abstract: A self-oscillating DC-DC buck converter with zero hysteresis is described. The converter comprises a comparator with a supply input, a non-inverting input to which a reference voltage is applied, an inverting input to which a feedback signal is applied, and an output to which a filter network is connected. The feedback signal is derived from the filter network and the output voltage of the converter is determined by the reference voltage. Connecting a filter network with an inductor and a capacitor to the output of the comparator and deriving the feedback signal from the filter network, results in an output of the comparator which is a DC output with a superimposed ripple. The level of the DC output is controlled by the reference voltage applied to the non-inverting input of the comparator, and the inductor current develops the ripple in the equivalent series resistance of the load circuit connected to the comparator output. The ripple can be regarded as the ramp signal in a conventional DC-DC converter.