Patents Represented by Attorney William, Morgan & Amerson
  • Patent number: 6838977
    Abstract: A method of inventory management is described. Upon activation of a button on a wireless device, the wireless device having a light source and a transceiver with a unique media address corresponding to a unique product, the device broadcasts a first signal including an order command and the unique media address by the transceiver via a wireless medium. A central controller then receives the first signal, identifies the unique media address included in the first signal, and using a database, identifies the unique product associated with the unique media address.
    Type: Grant
    Filed: March 7, 2001
    Date of Patent: January 4, 2005
    Assignee: Symbol Technologies, Inc.
    Inventors: Robert K. T. Chen, Mark E. Depperschmidt, James E. Lee, Jr., Patrick Gray
  • Patent number: 6703278
    Abstract: A method of forming oxide layers of different thickness on a substrate is described, wherein the oxide layers preferably serve as gate insulation layers of field effect transistors. The method allows to form very thin, high quality oxide layers with a reduced number of masking steps compared to the conventional processing, wherein the thickness difference can be maintained within a range of some tenths of a nanometer. The method substantially eliminates any high temperature oxidations and is also compatible with most chemical vapor deposition techniques used for gate dielectric deposition in sophisticated semiconductor devices.
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: March 9, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Karsten Wieczorek, Falk Graetsch, Stephan Kruegel
  • Patent number: 6586311
    Abstract: A method is provided, the method comprising forming a buffer layer above a structure layer, and forming a dielectric layer above the buffer layer. The method also comprises patterning the dielectric layer to form a salicide block above a portion of the structure layer protecting the portion from a subsequent salicidation. A device is also provided, the device comprising a buffer layer above a structure layer and a dielectric layer above the buffer layer. The dielectric layer is patterned to form a salicide block above a portion of the structure layer to protect the portion from a subsequent salicidation.
    Type: Grant
    Filed: April 25, 2001
    Date of Patent: July 1, 2003
    Assignee: Advanced Micro Devices, Inc.
    Inventor: David Donggang Wu
  • Patent number: 6303486
    Abstract: A method is provided for forming a copper interconnect, the method including forming a first dielectric layer above a structure layer, forming a first opening in the first dielectric layer, and forming a first copper structure in the first opening. The method also includes forming a sacrificial dielectric layer above the first dielectric layer and above the first copper structure, forming a second opening in the sacrificial dielectric layer above at least a portion of the first copper structure, and forming a second copper structure in the second opening, the second copper structure contacting the at least the portion of the first copper structure. The method further includes removing the sacrificial dielectric layer above the first dielectric layer and adjacent the second copper structure, and forming the copper interconnect by annealing the second copper structure and the first copper structure.
    Type: Grant
    Filed: January 28, 2000
    Date of Patent: October 16, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Stephen Keetai Park
  • Patent number: 6210211
    Abstract: In one aspect of the present invention, an apparatus for retaining an electrical connector is provided. The apparatus includes a tray adapted to receive an electrical device having a flexible connector coupled thereto. The tray is moveable between first and second positions. A spring extends between the tray and the flexible connector. The spring urges the flexible connector into a serpentine configuration in the first tray position.
    Type: Grant
    Filed: September 3, 1999
    Date of Patent: April 3, 2001
    Assignee: Compaq Computer Corporation
    Inventors: Gary Landrum, Michael Owens
  • Patent number: 6114229
    Abstract: A method is provided for controlling the critical dimensions of a polysilicon gate electrode, and for improving transistor drive current control. The method involves subjecting the gate structure of a transistor to a thermal treatment process in the presence of hydrogen gas. The thermal treatment process is performed subsequent to gate etching and photoresist mask removal, and provides gate electrodes having a more homogeneous linewidth, thereby improving transistor performance.
    Type: Grant
    Filed: November 20, 1998
    Date of Patent: September 5, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Frederick N. Hause, Mark I. Gardner, Charles E. May
  • Patent number: 6074840
    Abstract: Disclosed are novel nucleic acid and peptide compositions comprising latent TGF.beta. binding proteins (LTBPs). Also disclosed are methods of using LTBP-2 and LTBP-3 peptides and the DNA segments which encode them.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: June 13, 2000
    Assignee: The Regents of The University of Michigan
    Inventors: Jeffrey Bonadio, Wushan Yin