Abstract: The present invention provides a method of forming a transistor. The method includes forming a first layer of a first semiconductor material above an insulation layer. The first semiconductor material is selected to provide high mobility to a first carrier type. The method also includes forming a second layer of a second semiconductor material above the first layer of semiconductor material. The second semiconductor material is selected to provide high mobility to a second carrier type opposite the first carrier type. The method further includes forming a first masking layer adjacent the second layer and etching the second layer through the first masking layer to form at least one feature in the second layer. Each feature in the second layer forms an inverted-T shape with a portion of the second layer.

Abstract: In sophisticated semiconductor devices including copper-based metallization systems, a substantially aluminum-free bump structure in device regions and a substantially aluminum-free wire bond structure in test regions may be formed on the basis of a manufacturing process resulting in identical final dielectric layer stacks in these device areas. The number of process steps may be reduced by making a decision as to whether a substrate is to become a product substrate or test substrate for estimating the reliability of actual semiconductor devices. For example, nickel contact elements may be formed above copper-based contact areas wherein the nickel may provide a base for wire bonding or forming a bump material thereon.

Abstract: A gate electrode structure may be formed on the basis of a silicon nitride cap material in combination with a very thin yet uniform silicon oxide based etch stop material, which may be formed on the basis of a chemically driven oxidation process. Due to the reduced thickness, a pronounced material erosion, for instance, during a wet chemical cleaning process after gate patterning, may be avoided, thereby not unduly affecting the further processing, for instance with respect to forming an embedded strain-inducing semiconductor alloy, while nevertheless providing the desired etch stop capabilities during removing the silicon nitride cap material.

Abstract: High-k metal gate electrode structures are formed on the basis of a threshold adjusting semiconductor alloy formed in the channel region of one type of transistor, which may be accomplished on the basis of selective epitaxial growth techniques using an oxide hard mask growth mask. The hard mask may be provided with superior thickness uniformity on the basis of a wet oxidation process. Consequently, this may allow re-working substrates prior to the selective epitaxial growth process, for instance in view of queue time violations, while also providing superior transistor characteristics in the transistors that do not require the threshold adjusting semiconductor alloy.

Abstract: A method for compensating a transceiver for impairments includes transmitting a plurality of partial bandwidth training signals using a transmitter. A plurality of response signals of a receiver having a bandwidth and exhibiting receiver impairments is captured. Each response signal is associated with one of the partial bandwidth training signals. Each of the partial bandwidth training signals is associated with a portion of the receiver bandwidth. A plurality of partial compensation filters is generated based on the plurality of response signals. Each partial compensation filter is associated with one of the response signals. The partial compensation filters are combined to configure a receiver compensation filter operable to compensate for the receiver impairments.

Abstract: By recessing drain and source regions, a highly stressed layer, such as a contact etch stop layer, may be formed in the recess in order to enhance the strain generation in the adjacent channel region of a field effect transistor. Moreover, a strained semiconductor material may be positioned in close proximity to the channel region by reducing or avoiding undue relaxation effects of metal silicides, thereby also providing enhanced efficiency for the strain generation. In some aspects, both effects may be combined to obtain an even more efficient strain-inducing mechanism.

Abstract: A method includes designating a plurality of wafers as members of a group. A first subset of the wafers is housed in a first wafer pod and a second subset of the wafers is housed in a second wafer pod. The first wafer pod is routed to a first tool, and at least a first operation is performed on the wafers in the first subset using the first tool. The second wafer pod is routed to a second tool, and the first operation is performed on the wafers in the second subset using the second tool. The wafers in the first and second subsets are consolidated following the performing of the first operation.

Abstract: In sophisticated integrated circuits, an electronic fuse may be formed such that an increased sensitivity to electromigration may be accomplished by including at least one region of increased current density. This may be accomplished by forming a corresponding fuse region as a non-linear configuration, wherein at corresponding connection portions of linear segments, the desired enhanced current crowding may occur during the application of the programming voltage. Hence, increased reliability and more space-efficient layout of the electronic fuses may be accomplished.

Abstract: The present invention provides embodiments of a capacitor and a method of forming the capacitor. The capacitor includes one or more trenches formed in a semiconductor layer above a substrate. The trench includes dielectric material deposited on the trench walls and a conductive fill material formed within the trench and above the dielectric material. The capacitor also includes one or more first doped regions formed adjacent the trench(es) in the semiconductor layer. The first doped region is doped with a first type of dopant. The capacitor further includes one or more second doped regions formed adjacent the first doped region(s) in the semiconductor layer. The second doped regions are doped with a second type of dopant that is opposite to the first type of dopant.

Abstract: The present invention provides a method of assigning cell identifiers to a plurality of cells. The method includes detecting cells within a selected distance from a first cell in the plurality of cells. The distance is selected to encompass portions of neighbor cells of the first cell and neighbor-of-neighbor cells of the first cell. The method also includes assigning a first cell identifier to the first cell. The first cell identifier is different than cell identifiers assigned to the cells detected within the selected distance from the first cell.

Abstract: Methods and apparatuses for active heave compensation, the method, in certain aspects, including the steps of: (a) measuring with a measurement device (44) the heave of a vessel (10) and outputting a heave signal representative thereof; (b) using said heave signal to compensate for said heave by moving a connection device (20) relative to said vessel (10) as a function of said heave signal, whereby movement due to said heave of a load attached to said vessel via the connection device is reduced; said heave signal comprising errors induced by said measurement device (44) whereby accuracy of said compensation is reduced; (c) processing said heave signal so as to reduce said errors and outputting an adjusted heave signal; and (d) using said adjusted heave signal to move said connection device (20) to compensate for said heave.

Abstract: Floating systems for well operations are disclosed with a height-adjustable crown assembly movably connected to a derrick; in one aspect, movable within the derrick by movement apparatus; and, in one aspect, movable with a motion compensator. This abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure and is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims, 37 C.F.R. 1.72(b).

Abstract: An apparatus includes a plurality of data lines defining a data bus for communicating data. A controller is operable to communicate a plurality of data transfers over the data bus using a plurality of data time slots, wherein for at least a subset of the data time slots the controller is operable to communicate an associated data bus inversion indicator indicating that bits communicated during the associated data time slot are inverted, the data bus inversion indicators for the subset of the data transfers are grouped into a data bus inversion vector, and the controller is operable to communicate a global data bus inversion indicator indicating an inversion of the data bus inversion vector.

Abstract: In a replacement gate approach, the dielectric cap layers of the gate electrode structures are removed in a separate removal process, such as a plasma assisted etch process, in order to provide superior process conditions during the subsequent planarization of the interlayer dielectric material for exposing the sacrificial gate material. Due to the superior process conditions, the selective removal of the sacrificial gate material may be accomplished with enhanced uniformity, thereby also contributing to superior stability of transistor characteristics.

Abstract: A method for performing metallic line testing on a communication system is provided. The communication system includes an isolation transformer disposed between a provider circuit operable to provide a digital subscriber line signal and a subscriber circuit. The isolation transformer has a center tap. A test signal is injected at the center tap. A response of the subscriber circuit to the test signal is sensed.

Abstract: In sophisticated semiconductor devices including transistors having a high-k metal gate electrode structure, disposable spacers may be provided on the encapsulating spacer element with a reduced width so as to not unduly increase a lateral offset of a strain-inducing material to be incorporated into the active region. For this purpose, a multi-layer deposition may be used in combination with a low pressure CVD process.

Abstract: The present invention provides a method and apparatus for multiplexing code division and frequency division transmissions. One embodiment of the method includes accessing at least one first symbol and at least one second symbol, encoding the at least one first symbol according to a frequency division protocol, and encoding the at least one second symbol using a coding sequence having a cyclic correlation property. The method also includes transmitting a radiofrequency signal indicative of the at least one encoded first symbol and the at least one encoded second symbol.

Abstract: A method for installing rig structure (e.g. cabin, house, a doghouse) on a drilling rig, the method including: connecting support apparatus to a substructure of a drilling rig, supporting a drilling floor; moving a movement apparatus supporting a rig structure to position it adjacent the support apparatus, by moving movement apparatus on ground adjacent the substructure, moving the support apparatus into a connecting orientation with respect to the structure; connecting raising apparatus to the structure, the raising apparatus connected to the support apparatus; raising the structure up to the drill floor with the raising apparatus; and securing the structure to the support apparatus. This abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure and is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims, 37 C.F.R. 1.72(b).

Abstract: A computer-implemented method and an apparatus for use in a computing apparatus are disclosed. The method includes determining a context and a data requirement for a candidate action to be selected, the selection specifying an action in a workflow; and filtering the candidate actions for relevance in light of the context and the data requirement. The apparatus, in a first aspect, includes a program storage medium encoded with instructions that, when executed by a computing device, performs the method. In a second aspect, the apparatus includes a computing apparatus programmed to perform the method.

Abstract: In sophisticated transistor elements, long-term threshold voltage shifts in transistors comprising a threshold adjusting semiconductor alloy may be reduced by reducing the roughness of an interface formed between the threshold adjusting semiconductor material and the gate dielectric material. To this end, a portion of the threshold adjusting semiconductor material may be oxidized and may be removed prior to forming the high-k dielectric material.