Abstract: An IGFET is presented which includes a relatively low resistance path across the source-substrate junction to prevent parasitic bipolar effects while maintaining high component density in integrated circuits. The low resistance path across the source-substrate junction is formed by various methods including damaging the crystal structure at the junction interface, supplementing the damaged junction with a heavily doped region underlying the source region and spiking metallurgy. A particular application of the invention allows the prevention of latchup in CMOS devices. The invention also allows the source region of an IGFET to serve the dual functions of a source for a MOSFET as well as an ohmic contact to the underlying well or substrate.

Abstract: A nonlinear optical medium wherein the optical index of refraction is a function of the intensity of light irradiating the medium, is employed in various devices to affect at least a portion of an incoming light beam by refracting or reflecting that portion of the light and thereby reduce the amount of light falling on an object. The nonlinear optical medium is employed in a resonator optical bistable device, in a self-bending approach and in a self-defocusing approach to provide the protective function. The spatial profile of light intensity of the incoming light can be shaped prior to the incoming light irradiating the nonlinear medium or the nonlinear medium itself can be shaped to provide the path altering function. A laser hardened device with ultra fast switching time, a large dynamic range and passive operation is a preferred application of the present invention.

Abstract: Information on the shape of an object is extracted by generating an image of the object, encoding and ordering the boundary points of the image, selecting points on the outermost portions of the boundary, partitioning the boundary at the selected points into segments of either a first or second kind wherein the segments are distinguished according to a selected smoothness test, and segments of the first kind are smoother than segments of the second kind, partitioning each segment of the second kind into segments of the first or second kind according to the above test, and continuing the partitioning of each of the segments of the second kind into segments of the first or second kind until no further segments of the second kind are identified. An apparatus for performing the above steps is also disclosed.

Abstract: An integrating analog-to-digital converter having an operational amplifier serving as an integrator and as a comparator.

Abstract: Disclosed is a pressure transducer comprising a pressure sensitive silicon die having a front side exposing piezoresistive means and comprising means for flip-chip mounting the die to a pressure vessel. The transducer further comprises a pressure vessel having an aperture, the pressure vessel comprising means for flip-chip mounting the die over the aperture. The die is flip-chip mounted over the aperture in the pressure vessel, and there is a hermetic seal between the pressure vessel and the die.

Abstract: A memory system having voltage level circuit switching portions operated between signal lines stabilized by additional capacitance.

Abstract: A pressure compensated, fiber optic coupler for use underwater includes a water impermeable housing have first and second apertures to receive the respective optical fibers. One fiber is permanently held by the seal to the first aperture. The other fiber is inserted through the second aperture which is sealed by a conformable seal which is biased closed when no fiber is inserted through it. An incompressible, refraction of index matched fluid fills the interior of the housing to provide pressure compensation. The conformable seal is conveniently constructed of flexible neoprene and the housing is preferably titanium.

Abstract: A device for converting time varying signals which represent sin .theta. and cos .theta. of an angle .theta., where can take on values over a range, to an n bit digital signal. The range is typically 2.pi. radians and is segmented into 2.sup.n+1 -4 segments. The segments are mapped into 2.sup.n -1 amplitudes, and are encoded as the n bit digital signal. The invention is particularly useful as an angle digitizer where .theta. represents the phase difference between an input signal and a reference signal. As an angle digitizer, harmonic rejection is enhanced by the efficient use of the n bits to distinguish amplitude states as opposed to distinguishing merely phase states.

Abstract: A memory cell includes two active load, pnp transistors, and two npn switching transistors. The collector and base regions of the switching transistors are cross coupled. Each of the load transistors have two collectors, with the base of each load transistor directly connected to only one of its two collectors. The additional collector prevents the switching transistors from heavily saturating and thus increases the speed of operation of the cell.

Abstract: A magnetic solid state device, such as a magnetoresistive memory cell, includes first and second layers of magnetoresistive material. The first and second layers are separated by a third layer which prevents exchange coupling between the magnetic dipoles of the first and second layers. The first, second and third layers are formed as a strip. A fourth layer of a resistive material, such as nitrogen doped tantalum, overlies the first layer. The fourth layer includes spaced, raised portions over which electrically conductive material, such as TiW, may be formed on top of the raised portions.

Abstract: A circuit receives either a composite voltage, which is the sum of a signal voltage and a noise voltage, or the noise voltage. A switching arrangement is used to charge a first capacitor to the composite voltage, and a second capacitor to the noise voltage. The opposite poles of the first and the second capacitors are connected after they are charged, to generate an output voltage which is proportional to the signal voltage alone.

Abstract: A memory cell having a plurality of storage structures in a differential arrangement. Two multilayered magnetoresistive memory cells are placed in a bridge arrangement with two impedance devices. The memory cells have one bridge juncture in common. Switches are connected to at least two of the four bridge junctures to permit the writing or reading of the magnetic state of the storage cells. The bridge arrangement combined with the appropriate switching action allows for a near doubling of the magnitude of the output sense signal while reducing the noise component of such signal.

Abstract: A very high speed, low power integrated interface circuit using GaAs or InP technology is provided for converting small digital voltage swings to larger swings which are particularly suitable for analog control signals. The preferred embodiments employ solely depletion mode MESFETS and Schottky diodes in Schottky diode field effect logic (SDFL) configurations.

Abstract: A method of mapping at least a portion of a magnetic field with an interferometer is presented. The interferometer includes an optical fiber clad with a magnetostrictive material. The approximate direction of the magnetic field lines are determined and the optical fiber is placed substantially transverse to the magnetic field lines. The output of the interferometer is recorded for various positions of the optical fiber. The fiber can be maintained substantially transverse to the magnetic field lines during mapping, or the fiber can be positioned substantially transverse to the field lines to precisely determine the direction of field lines and substantially parallel to the field lines to determine field magnitude. In one embodiment the interferometer is adapted to produce a null output for a predetermined value of the integral of the magnetic field along the length of the optical fiber, and the optical fiber is of uniform construction.

Abstract: An output device is disclosed including a first light light guide having an input port and an output port; a second light guide adapted to allow light to be inserted into said first light guide at a first location in said first light guide; means for absorbing light propagating through a second location in said first light guide, said second location being between said input port and said first location; and means for allowing the detection of information concerning light propagating in said first light guide, said means for allowing detection being located between said input port and said first location. Four embodiments are presented, each being integrated optical devices adapted to provide fail safe protection when used in a bus line system.

Abstract: An improved topology for a multi-input Boolean logic circuit whereby the circuit can be realized in integrated circuit form while consuming less area on the semiconductor wafer and exhibiting lower parasitic capacitance than equivalent integrated circuits using conventional topology. Rather than employing what might be described as an "in-line" topology of the prior art, a ring topology is used wherein adjacent MESFET's share a common region for source, drain, or source/drain contacts and wherein the amount of second level interconnect required is minimized.

Abstract: A standard JFET or MESFET with a second gate is described. The second gate underlies the channel region, but is accessible from the same surface of the semiconductor body as are the other terminals of the transistor. Electrical signals are transmitted to the second gate by a heavily doped interconnect region. Isolation techniques prevent a voltage applied to this second gate from having a significant effect on adjoining electronic devices. Also described is a process for manufacturing such transistors using only steps which are present in a typical bipolar processing sequence.

Abstract: Field-effect transistor devices are provided having a relatively substantial capability to withstand reverse bias voltages. This capability is provided through providing shields in these devices near junctions in such devices which are subject to breakdown under large reverse bias voltages, these shields being operable at selected voltages. The device can also be provided having a relatively low "on" condition resistance between the source and drain terminals thereof by virtue of a geometrical design choice. A method for fabricating one such device is also disclosed.

Abstract: A substantially planar surface is provided over a silicon semiconductor device by depositing a silicate glass, heating the silicate glass so it reflows, bias sputtering a dielectric layer over the reflowed glass, depositing a photoresist over the dielectric layer and etching away the photoresist and enough of the dielectric to provide a substantially planar surface of the dielectric material. Quartz is the preferred dielectric material.

Abstract: A digital memory based on a memory cell having two magnetoresistive ferromagnetic film portions separated by an intermediate layer all of which are gradually narrowed at the ends thereof.Adjacent memory cells are preferrably arranged in a line with conductive junctions therebetween. The magnetic state of each cell can be sensed or set by providing currents of different magnitudes in conductive word lines which overlie the cells. The narrowed ends of the cells reduce demagnetizing effects which occur if the cell ends are abruptly terminated.