Abstract: A two-wired LED light adjusting system, for controlling the luminance adjustment for a LED lamp module. The light adjusting circuit includes a phase modulating circuit, a LED driving circuit and a controller. The phase modulating circuit generates a phase modulating voltage. The controller detects the phase modulating voltage of various waveforms. When the controller detects the phase modulating voltage of different waveforms, the controller controls the LED driving circuit to enable the LED lamp module to emit light of different luminance according to waveforms of the phase modulating voltage.

Abstract: A coding system includes an inter prediction block, a transform and quantization block, an encoding unit, and a reconstruction loop with an adaptive restoration block. The inter prediction block performs prediction on a current frame, the transform and quantization block performs transform and quantization processes on prediction residues, and the reconstruction loop reconstructs the current frame to generate the restored reconstructed samples. The adaptive restoration block performs restoration on processed data by considering a plurality of candidate restoration methods, selects one of the candidate restoration methods as a final restoration method, and generates adaptive restoration information corresponding to the final restoration method. The encoding unit encodes the prediction information and adaptive restoration information to generate an encoded bitstream.

Abstract: A touch panel comprises a substrate and a transparent conductive layer including a plurality of groups of first conductive patterns, second conductive patterns, and third conductive patterns, and a plurality of first wires, second wires, and third wires. Each group of first conductive patterns is arranged along a first direction. Each group of second conductive patterns is arranged along a second direction and located at a first side of the second direction. Each group of third conductive patterns is arranged along the second direction and located at a second side of the second direction. Each group of first conductive patterns, each group of second conductive patterns, and each group of third conductive patterns are electrically insulated to each other. Each second conductive pattern among each group of second conductive patterns has different areas, and each third conductive pattern among each group of third conductive patterns has different areas.

Abstract: SRAM writing system and related apparatus are provided. The writing system of the invention has a dummy replica writing circuit, a negative pulse controller and at least a normal writing circuit; each normal writing circuit includes a write driver and a negative pulse supplier. While writing, the dummy replica writing circuit drives a dummy replica bit-line, such that the negative pulse controller generates a negative pulse control signal according to level of the dummy replica bit-line. In each writing circuit, when the write driver conducts to connect an associated bit-line to a bias end for driving a level transition, the negative pulse supplier switches the bias end from an operation voltage to a different negative pulse voltage according to the received negative pulse control signal.

Abstract: A display panel having a repair structure utilizes floating repair lines integrated into the display panel. Each of the floating repair lines bridges across each of any two adjacent pixels so as to be used for the repair of open lines on scan lines, data lines and common lines in the display panel as required. The display panel of the present invention having a repair structure integrates each of the floating repair lines between each of any two adjacent pixels so as to form new substitutional signal transmission routes of various types of open lines. The substitutional signal transmission route is able to reduce the resistive-capacitive delay of the repaired display panel and the impedance of repaired lines, and avoid signal decay and distortion.

Abstract: A liquid crystal display includes a gate driver, a control circuit and a charge-sharing circuit. The control circuit provides a charge-sharing signal according to the parasitic capacitances at a first output end and a second output end in the gate driver. The charge-sharing circuit generates a third clock signal and a fourth clock signal by performing charge-sharing on a first clock signal and a second clock signal according to the charge-sharing signal. The third clock signal includes a signal falling edge which descends from a high level to a first level, and the fourth clock signal includes a signal falling edge which descends from the high level to a second level. The gate driver outputs a first gate driving signal and a second gate driving signal respectively at the first and the second output end according the third or the fourth clock signal.

Abstract: A method for managing a memory block is provided. In this method, a plurality of block tables having different storing priorities is provided. In addition, the number of error correction bits in the memory block is checked. Thereby, in the present invention, data is stored into the memory block in a block table according to the number of error correction bits in the memory block so that the sequence in which the memory block is used for storing data is determined.

Abstract: An infant-carrier docking station includes a support part and a carrier holder. The support part is disposed across on opposite handrails of a crib frame. The carrier holder is connected to the support part above the crib frame. The carrier holder can hold an infant carrier of a safety seat in a detachable way. A crib includes a bed frame and the infant-carrier docking station. The infant-carrier docking station is disposed across on opposite handrails of the bed frame. Therefore, the invention is convenient for a caregiver to directly move the infant carrier from any place else to the infant-carrier docking station without waking up the baby sleeping on the infant carrier.

Abstract: A method of making a metal capacitor includes the following steps. A dielectric layer having a dual damascene metal interconnection and a damascene capacitor electrode is provided. Then, a treatment is performed to increase the dielectric constant of the dielectric layer surrounding the damascene capacitor electrode. The treatment can be UV radiation, a plasma treatment or an ion implantation. Accordingly, the metal capacitor will have a higher capacitance and RC delay between the dual damascene metal interconnection and the dielectric layer can be prevented.

Abstract: A method of removing a spacer, a method of manufacturing a metal-oxide-semiconductor transistor device, and a metal-oxide-semiconductor transistor device, in which, before the spacer is removed, a protective layer is deposited on a spacer and on a material layer (such as a salicide layer) formed on the source/drain region and a gate electrode, such that the thickness of the protective layer on the spacer is smaller than the thickness on the material layer, and thereafter, the protective layer is partially removed such that the thickness of the protective layer on the spacer is approximately zero and a portion of the protective layer is remained on the material layer. Accordingly, when the spacer is removed, the material layer may be protected by the protective layer.

Abstract: A method of frame interpolation for frame rate up conversion method is provided. The method includes: determining a first adjusting value and a second adjusting value according to a target pixel in at least one of a first frame and a second frame; determining an interpolated pixel value of the target pixel in an interpolated frame between the first frame and the second frame according to the first adjusting value and a pixel value of the target pixel in one of the first and second frames; and adjusting a pixel value of the target pixel in one of the first and second frames according to the second adjusting value.

Abstract: A metal capacitor structure is disclosed. The metal capacitor structure includes: a dielectric layer having a first region and a second region, a dielectric constant of the dielectric layer in the second region being higher than a dielectric constant of the dielectric layer in the first region; a dual damascene metal interconnection positioned in the first region; and a damascene capacitor electrode positioned in the second region.

Abstract: A manufacturing method of a metal gate structure includes providing a substrate having at least a first metal oxide layer formed thereon, and transferring the surface of the first metal oxide layer into a second metal oxide layer. The first metal oxide layer includes a metal oxide (M1Ox) of a first metal (M1) and the second metal oxide layer includes a metal oxide ((M1M2Oy) of the first metal and a second metal (M2).

Abstract: A frame rate adjuster is utilized for adjusting a frame rate of a display according to the brightness of a frame. The frame adjuster comprises a frame counting circuit, a brightness-counting circuit, a brightness-determining circuit, and a frame rate selecting circuit. The frame counting circuit is utilized for determining if gray-level data of the frame are all transmitted and accordingly generating a frame trigger signal. The brightness counting circuit is utilized for generating a plurality of brightness-counting numbers according to the gray-level data of the brightness of the frame. The brightness-determining circuit is utilized for outputting a brightness-determining signal according to the frame trigger signal and the plurality of the brightness-counting numbers. The frame rate selecting circuit is utilized for selecting a reference frame rate among a plurality of reference frame rates so as to adjust the frame rate of the display.

Abstract: A liquid crystal display device includes a plurality of gate lines, a plurality of data lines, a pixel array, a gate driver, a timing controller, and an optimization circuit. Each pixel unit in the pixel array displays images according to the gate driving signal received from a corresponding gate line and the data driving signal received from a corresponding data line. According to an optimized reference value, the timing controller provides an output enable signal, based on which the gate driver outputs the gate driving signals. The optimization circuit receives a first grayscale data related to display images of a row of pixel units in a first driving period and a second grayscale data related to display images of the row of pixel units in a second driving period, and provides the optimized reference value according the difference between the first and second grayscale data.

Abstract: This invention provides a mold for injection molding and a method of manufacturing thereof. The method of manufacturing a mold for injection molding includes the following steps. At least one temperature control element is provided. The temperature control element is covered with a first material. The first material is mechanically processed to form a mold body with a cavity. The mold for injection molding includes a mold body, a temperature control element, and a heat insulating layer.

Abstract: A power-saving network apparatus includes a MAC and a PHY. The PHY includes a transmitter and a receiver. The transmitter executes the operations of: transmitting a data signal to a remote network apparatus according to output packets of the MAC when the transmitter enters a normal state; transmitting an idle signal to the remote network apparatus when the transmitter enters an idle state; transmitting an indication signal to the remote network apparatus to notify it to enter a low power state, wherein the indication signal is different from the idle signal; entering the idle state or the normal state from the low power state in response to at least one of a predetermined period and a transmitting enable signal.

Abstract: A transmit power control system includes: an output power estimator for estimating a transmit power of a transmitter; and a transmit power controller responsive to the output power estimator and to compare this with a requested power in order to calculate a target power which takes account of errors within the transmit power control system, and to vary a gain of an amplifier in a transmit signal path so as to reduce an error between the transmit power of the amplifier and the requested power.

Abstract: A linkage mechanism is configured between two relatively slidable first housing and second housing of a handheld device. The linkage mechanism can be actuated by a first actuator of the first housing when the second housing slides out at an opening status relative to the first housing. The linkage mechanism is actuated to rotate and then to drive a second actuator to slide on the second housing and the second actuator forces a supporter, which pivots to the second housing, to open at a predetermined angle relative to the second housing. The handheld device is made steady on a plane through the support provided by the opened supporter. When the handheld device slides in at a closing status, a restoring spring configured between the supporter and the second housing automatically folds the supporter.

Abstract: A frequency divider comprises a phase selector and a timing circuit. The phase selector is arranged to receive a plurality of input signals and a plurality of control signals and output a plurality of output signals according to the control signals, wherein a predetermined reference voltage and the input signals are selectively chosen to generate the output signals according to the control signals, and the input signals are of a same frequency but different phases. The timing circuit is arranged to receive the output signals and generate the control signals according to the output signals.