Abstract: A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An undercutting etch forms a bubble recess under the active area to partially vertically isolate the active area. A thermal oxidation completes the vertical isolation by use of a minifield oxidation process. The recess is filled to form a shallow trench isolation structure. An active device is also disclosed that is achieved by the process. A system is also disclosed that uses the active device.

Abstract: Integrated circuits, the key components in thousands of electronic and computer products, include interconnected networks of electrical components. The components are typically wired, or interconnected, together with aluminum wires. In recent years, researchers have begun using copper instead of aluminum to form integrated-circuit wiring, because copper offers lower electrical resistance and better reliability at smaller dimensions. However, copper typically requires use of a diffusion barrier to prevent it from contaminating other parts of an integrated circuit. Unfortunately, typical diffusion barrier materials add appreciable resistance to the copper wiring, and thus negate some advantages of using copper. Moreover, conventional methods of forming the copper wiring are costly and time consuming. Accordingly, the inventors devised one or more exemplary methods for making integrated-circuit wiring from materials, such as copper-, silver-, and gold-based metals.

Abstract: The invention includes a stacked open pattern inductor fabricated above a semiconductor substrate. The stacked open pattern inductor includes a plurality of parallel open conducting patterns embedded in a magnetic oxide or in an insulator and a magnetic material. Embedding the stacked open pattern inductor in a magnetic oxide or in an insulator and a magnetic material increases the inductance of the inductor and allows the magnetic flux to be confined to the area of the inductor. A layer of magnetic material may be located above the inductor and below the inductor to confine electronic noise generated in the stacked open pattern inductor to the area occupied by the inductor. The stacked open pattern inductor may be fabricated using conventional integrated circuit manufacturing processes, and the inductor may be used in connection with computer systems.

Abstract: A package coating is processed by applying a plurality of aqueous mixtures over a substrate. The aqueous mixtures each include a combination of pigments and binders. A packaging article is also disclosed that is made from the package coating on a substrate. Additionally, a packaging system is included that contains commercial product.

Abstract: An inventive security framework for supporting kernel-based hypervisors within a computer system. The security framework includes a security master, one or more security modules and a security manager, wherein the security master and security modules execute in kernel space.

Abstract: The present invention provides a method for reducing stroke-related tissue damage by treating a mammal with E-selectin. Preferably, this treatment induces E-selectin tolerance in the mammal. Another aspect of the invention is a method for inducing E-selectin tolerance in a mammal through intranasal administration of E-selectin, preferably including booster administrations. The present methods are especially adapted for use in patients at increased risk of stroke or who may become at increased risk of stroke.

Abstract: A method of packaging a die includes attaching the die to a substrate; underfilling the space between the die and the substrate with a first material, and placing a second material in contact with at least a portion of the die and the substrate after underfilling the space between the die and substrate with the first material. A system includes a semiconductor package having a substrate, a die attached to the substrate, an underfill material positioned between the die and the substrate, and a molding material in contact with at least a portion of the substrate and the die. A heat sink is also in thermal contact with the semiconductor package.

Abstract: Structures and methods are provided which include a selective electroless copper metallization. The present invention includes a novel methodology for forming copper vias on a substrate, including depositing a thin film seed layer of Palladium (Pd) or Copper (Cu) on a substrate to a thickness of less than 15 nanometers (nm). A number of via holes is defined above the seed layer. A layer of copper is deposited over the seed layer using electroless plating to fill the via holes to a top surface of the patterned photoresist layer. The method can be repeated any number of times, forming second, third and fourth layers of copper. The photoresist layers along with the seed layers in other regions can then be removed, such as by oxygen plasma etching, such that a chemical mechanical planarization process is avoided.

Abstract: A method and apparatus for making pad structures suitable for wirebonding and, optionally, also for solder-ball connections. Some embodiments include an electronics chip having a substrate with circuitry, a compliant electrically insulating layer deposited on at least a portion of the substrate, and an electrical connection pad, the pad having an electrical connection to the circuitry through an aperture in the insulating layer and a peripheral bonding zone region extending over the insulating layer. In some embodiments, the bonding zone is exclusively over the insulating layer outside of the aperture. In some embodiments, the pads are suitable for both solder-ball and wirebond connections. By making a wirebond connection to an area of a pad over the compliant insulating layer, the underlying circuitry is protected from ultrasonic energy of the bonding process.

Abstract: A device and method to detect and correct for clock duty cycle skew in a high performance microprocessor having a very high frequency clock. The device includes a delay chain circuit to delay the clock signal and to determine the presence of clock duty cycle skew. The device uses simple latches, flops, and phase-detectors to compare and identify the nature of the clock duty cycle skew. Simple logic is employed to measure and determine the amount and direction of de-skew to apply to the clock signal. After the de-skew operation, the clock duty cycle cycles used to control the execution of the microprocessor are of a more uniform time duration.

Abstract: The present invention relates to a method of increasing the live weight of poultry through the administration of a plasma product to the poultry through the animals' feed and/or water. The product is effective in increasing the live weight of poultry. The product is also surprisingly effective in increasing the yield of white meat to the detriment of dark meat.

Abstract: A communication unit operates in a wireless-networking environment and maintains a mapping for active channels and associated network identifiers. The communication unit may associate with a wireless network using the mapping for one or more of the active channels having a selected network identifier. For associations and reassociations with wireless networks, the communication unit may selectively scan the channels having mapping stored in a table to more quickly identify active channels and thereby reduce scan time. In some embodiments, an access point may perform channel-width measurements and radar detection using the bitmap.

Abstract: Systems and methods for determining the coronary sinus vein branch location of a left ventricle electrode are disclosed. The systems and methods involve detecting the occurrence of electrical events within the patient's heart including sensing one or more of the electrical events with the electrode and then analyzing the electrical events to determine the electrode's position. The determination of electrode position may be used to automatically adjust operating parameters of a VRT device. Furthermore, the determination of electrode position may be made in real-time during installation of the electrode and a visual indication of the electrode position may be provided on a display screen.

Abstract: During formation of an ad hoc group, the transmit power level of a user device within a wireless communication network is reduced. Potential group members are thus identified within an immediate vicinity of the user device.

Abstract: The present invention relates to a mobile crane boom having a self-sufficient energy supply arranged on it for supplying hydraulic energy to at least one hydraulic load arranged on the mobile crane boom. The supply of the hydraulic load arranged on the mobile crane boom is therefore not carried out by means of a hydraulic unit arranged on the revolving superstructure of the crane, which provides the hydraulic energy to each hydraulic load via hoses, but by means of a hydraulic unit which is arranged in the upper reaches of the mobile crane boom or in the area of the linkage of any second boom section. By arranging the hydraulic unit directly on the boom, the hoses normally required for supplying the hydraulic loads can be eliminated.

Abstract: A clock synchronization circuit (200, FIG. 2) includes a signal selector (202), phase detector (204), and delay line (206). The signal selector compares an external clock signal (220) and a feedback signal (222) to evaluate the jitter present in the external clock signal. When the jitter falls within an acceptable range, the circuit operates in DLL mode. In DLL mode, the external clock signal is provided to the delay line, and the delayed external signal is output (224) from the circuit. If the jitter falls outside the acceptable range and the circuit is locked, the circuit is switched to PLL mode. In PLL mode, a clock signal based on the feedback signal is provided to the delay line, and the delayed feedback signal is output from the circuit. The PLL mode is only allowed to operate briefly before switching the circuit back into DLL mode.

Abstract: In order to provide a compact loop antenna, for use in an inductive read/write apparatus, capable of extending a communication range even if the antenna area or power supply thereto is constrained, a compact loop antenna, for use in an inductive read/write apparatus, comprises two layers of loop antennas, each thereof comprising a printed circuit board 2 for featuring a loop pattern 1, a loop pattern 1 formed by an etching process on the printed circuit board 2, and a start terminal 3 and a end terminal 4 for supplying power for signal transmission and outputting a received signal and each thereof maintaining a predetermined distance from each other.

Abstract: An apparatus and a system, as well as a method and article, may operate to include repeating first data to provide first repeated data and deleting second repeated data to provide second data according to a programmed standard included in a first apparatus and selected from a plurality of reprogrammable standards.

Abstract: A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Also shown is a gate oxide with a conduction band offset in a range of approximately 5.16 eV to 7.8 eV. Gate oxides formed from elements such as zirconium are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit the layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.

Abstract: Logic circuit for generating carry or sum bit output by combining binary inputs, includes bit level carry generate and propagate function logic receiving binary inputs and generating bit level carry generate/propagate function bits for binary inputs by respectively logically AND and OR combining respective bits of binary inputs; logic generating high output if a carry is generated out of a first group of most significant bits of binary input or if carry propagate function bits for the most significant bits are all high; logic for receiving bit level carry generate and propagate function bits for binary inputs to generate high output if any of carry generate function bits for the most significant bits are high or if carry is generated out of another group of least significant bits of binary input; and logic for generating the carry or sum bit output by combining outputs of the two logics.