Abstract: A time measurement circuit (100) measures a time interval between two events. The time measurement circuit (100) includes two digital phase counters (10' and 10"), a period counter (210), and a digital calculator (310). The first digital phase counter (10') converts a time interval from a leading edge of a start signal to a leading edge of clock signal following the start signal into a first binary number. The second digital phase counter (10") converts a time interval from a leading edge of a stop signal to a leading edge of clock signal following the stop signal into a second binary number. The period counter (210) converts a time interval between the two leading edges of the clock signal into a third binary number. The digital calculator (310) combines the three binary numbers to generate a number representing the time interval between the start signal and the stop signal.

Abstract: A method for forming a metal pattern on a substrate (11) includes forming a dielectric stack (14) on a major surface (12) of the substrate (11) and forming a mask (22) on the dielectric stack (14). The dielectric stack (14) includes an aluminum nitride layer (16) serving as an etch stop layer between two dielectric layers (15, 17). An opening is formed in the dielectric stack (14) via successive etching. The etching of the dielectric layer (15) between the aluminum nitride layer (16) and the substrate (11) undercuts the aluminum nitride layer (16). A metal layer (30) is deposited on the major surface through the opening via sputtering. The metal layer (30) on the major surface is distinctively separated from a metal layer (34) on the edge of the opening. The mask (22) is dissolved in a solvent, thereby lifting-off a metal layer (34) deposited on the mask (22).

Abstract: A method for encoding a state machine includes performing a state transition probability analysis (11) to identify hot states (12) and cold states. Then hot (13) and cold (14) states are encoded. The encoding minimizes the expected bit flip (EBF). In addition, a local encoding exploration may be performed to further optimize the encoding of the state machine for area and power consumption. The local encoding exploration preserves the EBF.

Abstract: A semiconductor fuse device is formed of a conductive semiconductor substrate (11) having a top surface and a bottom surface. A layer (12) of dielectric material is provided on a portion of the top surface and a first conductive layer (15) is formed wholly on a first portion of the layer (12) of dielectric material and forms a first contact of the device. A second conductive layer (14) is formed on a second portion of the layer (12) of dielectric material spaced from the first portion and extends to contact the top surface of the substrate (11). A fuse portion (16) is formed wholly on the layer (12) of dielectric material and extends between and in electrical contact with the first and second conductive layers (14, 15). The bottom surface of the substrate (11) provides a second contact of the device, so that only one wire bond is necessary.

Abstract: The intermediate frequency (IF) amplifier (10) of the invention comprises a differential stage (40) having transistors (41, 42) serially coupled to inductive loads (31, 32). There is only one point at common sources (node 45) which is sensitive to spikes. A feedback stage (60) extracts a common mode spike component at spike frequency (f.sub.S) from the output and returns a feedback signal to the sensitive point (node 45). Comparing to traditional differential amplifiers, the common mode rejection at resonance frequencies (f.sub.R) can be 30 times higher. This makes the amplifier (10) spike insensitive and suitable for the integration into mixed analog-digital chips, such as DSP chips, where the analog portions operate in the same frequency range as the digital portions.

Abstract: A differential amplifier (10) includes three unilateral field effect transistors (12, 14, 16) formed in a common well (40) of a semiconductor material. Each of the three unilateral field effect transistors (12, 14, 16) has an asymmetric channel doping profile. The performance of the differential amplifier (10) is significantly improved by properly orienting the three unilateral field effect transistors (12, 14, 16).

Abstract: A battery protection system (20) controls a process for charging a battery pack (15). A hysteresis comparator (54) senses a charging current flowing through the battery pack (15) and switches off a charging switch (31) to interrupt the charging current when the charging current reaches an upper limit. A transient current is then generated by an inductor (34). The hysteresis comparator (54) senses the transient current flowing through the battery pack (15) and switches on the charging switch (31) to regenerate the charging current when the transient current decreases substantially to zero. Periodically, a battery monitoring circuit (40) switches off the charging switch (31) and measures an open circuit voltage across each battery cell in the battery pack (15). In response to the open circuit voltage of a battery cell reaching a fully charged voltage, the battery monitoring circuit (40) switches off the charging switch (31) to terminate the charging process.

Abstract: A method for forming a semiconductor fuse device (23) having a fuse element (20) for an igniter device, comprises the steps of providing a semiconductor substrate (12), forming an insulator layer (14) on the semiconductor substrate, forming a single active layer (16) on the insulator layer, having a predetermined depth (18) of greater than 4 microns and patterning and etching the active layer to form the fuse element (20). Preferably, the forming a single active layer step includes the step of atomic bonding an active layer to the insulator layer.

Abstract: A time measurement circuit (100) measures a time interval between two events. The time measurement circuit (100) includes two digital phase counters (10' and 10"), a period counter (210), and a digital calculator (310). The first digital phase counter (10') converts a time interval from a leading edge of a start signal to a leading edge of clock signal following the start signal into a first binary number. The second digital phase counter (10") converts a time interval from a leading edge of a stop signal to a leading edge of clock signal following the stop signal into a second binary number. The period counter (210) converts a time interval between the two leading edges of the clock signal into a third binary number. The digital calculator (310) combines the three binary numbers to generate a number representing the time interval between the start signal and the stop signal.

Abstract: A semiconductor on insulator structure (50) includes a silicon layer (30) formed on an insulating substrate (20). The silicon layer (30) is partitioned into two sections (32, 34) which are electrically isolated from each other. The thickness of the silicon layer (30) in a first section (32) of the silicon layer (30) is adjusted independently from the thickness of the silicon layer (30) in a second section (34) of the silicon layer (30). Independently adjusting the thickness of the silicon layer (30) allows optimizing the performance of semiconductor devices (60, 80) fabricated in the first and second sections (32, 34) of the semiconductor on insulator structure (50).

Abstract: A nonvolatile memory cell (10) includes a single n-channel insulated gate FET (11) having a single floating gate (12). The FET (11) operates asymmetrically in a sense that the capacitance of a parasitic gate-source capacitor (24) is smaller than the capacitance of a parasitic gate-drain capacitor (26). The asymmetric condition is achievable either by fabricating the FET (11) as an asymmetric structure (30, 60) or by adjusting the capacitance of the parasitic capacitors (24, 26) through terminal biasing when the FET (11) is a short channel device. The potential of the floating gate (12) is controlled by biasing the source (14), drain (16), and substrate (18) of the FET (11). The cell (10) is programmed by moving charge onto the floating gate (12) via hot carrier injection, erased by moving charge from the floating gate (12) via tunneling, and read by sensing the conductive state of the FET (11).

Abstract: An amplifier (40) includes a biasing element (59) which establishes a quiescent current in two transistors (62, 72). An input voltage signal is converted to an input current signal by a voltage to current converting element (65). The input current signal differentially modulates the currents in the two transistors (62, 72). The differentially modulated currents generates differentially modulated voltages across two diodes (76, 78). Two buffers (83, 87) generates a differential output voltage signal at two output terminals (77, 79) of the amplifier (40) by shifting the differentially modulated voltages across the two diodes (76, 78). The output signal of the amplifier (40) has a low DC offset. The gain of the amplifier (40) is adjusted by adjusting the quiescent current in the two transistors (62, 72).

Abstract: A control module (11) in an airbag system (10) supplies electrical energy to and communicates with remote modules (20A-20N) through a two-wire connection. The supplied electrical energy is partially used to operate the remote modules (20A-20N) and partially stored within the remote modules (20A-20N) for deploying squibs (22A-22N). The control module (11) sends command signals to the remote modules 20A-20N) via voltage excursions between a high and an intermediate voltage levels. The remote modules (20A-20N) send signals to the control module (11) via current excursions. When an accident situation is detected, the voltage across the two-wire connection is lowered to a low voltage level, thereby interrupting a normal operation of the airbag system (10). The control module (11) then sends out firing signals via voltage excursion between the intermediate and low voltage levels. The remote modules (20A-20N) decode the firing signals and deploy the squibs (22A-22N) to inflate airbags.

Abstract: A programmable array (10) includes an array (11) of transistor cells, output cells (26, 28, 32, 34), and two internal power busses (17, 18) which are coupled to the array (11) of transistor cells. The programmable array also includes eight output power busses (35, 36, 37, 38, 41, 42, 43, 44) coupled to the output cells (26, 28, 32, 34). The two internal power busses (17, 18) are coupled to two corresponding output power busses (35, 36) via two coupling switches (55, 56). Further, the output power busses (35, 36, 37, 41, 42, 43, 44) are coupled to each other via eight switches (45, 46, 47, 48, 51, 52, 53, 54). Different power bus routings of the programmable array (10) are realized by controlling the two coupling switches (55, 56) and the eight switches (45, 46, 47, 48, 51, 52, 53, 54).

Abstract: A power amplifier (50) includes two transistors (11, 21) and a dynamic biasing circuit (52). The dynamic biasing circuit (52) uses a sampling circuit (54) to generate a bias adjusting signal proportional to the amplitude of an AC signal at a drain electrode of the first transistor (11). The bias adjusting signal is combined with a constant voltage bias signal to generate a dynamic biasing signal applied to a gate electrode of the second transistor (21). As the gain of the first transistor (11) decreases, the amplitude of the AC signal at its drain electrode decreases. Thus, the dynamic biasing circuit (52) generates a lower dynamic biasing signal at the gate electrode of the second transistor (21), thereby decreasing a quiescent drain current in the second transistor (21) and improving the efficiency of the amplifier (50) at low output power levels.

Abstract: An object of the present invention is to contribute to increase of storage capacity of a memory and to cope with an nonlinear parasitic resistance.The non-volatile memory have a cell applying to multi-bit data by means of a double layered floating gate architecture. The cell comprises: heavily doped layers (drains 3.sub.0 -3.sub.2 and source 2) being formed separated from each other along an arrangement direction L in a semiconductor substrate; a first floating gate 4A being disposed along a direction orthogonal to the direction L between the drains and source above the semiconductor substrate; second floating gates 4B.sub.1, 4B.sub.2 which respectively extend across the first floating gate above the first floating gate and lie along the direction L, close to the drain; program gates 6.sub.1, 6.sub.2 disposed correspondingly to one of the second floating gates; and a control gate 5 extending across the gate 4A above the gate 4A and being disposed along the direction L, close to the source.

Abstract: A semiconductor structure (20) includes a silicon layer (16) formed on an oxide layer (14). Gettering sinks (31, 32) are formed in the silicon layer (16). Lateral gettering is performed to effectively remove impurities from a first section (26) of the semiconductor layer (16). An insulated gate semiconductor device (40) is then formed in semiconductor layer (16), wherein a channel region (55) of the device (40) is formed in the first section (26) of the semiconductor layer (16). A gate dielectric layer (42) of the device (40) is formed over a portion of the first section (26) after the lateral gettering process, thereby enhancing the integrity of the gate dielectric layer (42).

Abstract: In a method for operating an electric motor especially a permanent magnet motor, the voltage applied to the windings of the stator of the motor are commuted electronically. The timing of the commutation events is determined by sensing and low pass filtering the differential voltages between the windings and detecting the zero crossings of the filtered differential voltages. At the time the zero crossings take place or within a short time afterwards the commutation events take place.

Abstract: An optical housing (30) includes an optical pedestal (10), a light-blocking mask (31), and a translucent light diffuser (32). The optical housing (30) is used to inspect a work piece (51) placed on a top surface (21) of the optical pedestal (10). Diffusive light is transmitted from the translucent light diffuser (32) into the optical pedestal (10) via a portion of an optically polished bottom surface (11) that is uncovered by the light-blocking mask (31). In the optical pedestal (10), light is reflected by an optically polished inclined surface (23) and refracted by another optically polished inclined surface (25). When light is transmitted away from the optical pedestal (10) after being refracted, it is a collinear light beam and substantially parallel to the top surface (21) of the optical pedestal (10).

Abstract: An electronic device package (10) is resistant to rupture at high temperatures. The electronic device package (10) includes a cap (14) having side-walls (18) coupled to a support structure (11) via an adhesive (15). The cap (14) is permeable to gases including water vapor. The side-walls (18) of the cap (14) are made of a porous ceramic material which absorbs a portion of the adhesive (15) via capillary action while curing the adhesive (15).