Abstract: An output circuit (40) includes pull-up transistor (12), two pull-down transistors (14, 16), and a noise suppression circuit (58). When an input node (50) of the output circuit (40) switches to a logic high voltage, the pull-up transistor (12) is switched off. A first transistor (22) in the noise suppression circuit (58) is switched on, discharges a capacitive load (32) coupled to an output node (60) of the output circuit (40), and charges a capacitor formed by a second transistor (24) in the noise suppression circuit (58). After a time delay, the two pull-down transistors (14, 16) are switched on sequentially and establish two current paths from the output node (60) to ground (25). Then, a third transistor (56) in the noise suppression circuit (58) is switched on, discharges the capacitor (24), and establishes a third current path from the output node (60) to ground.

Abstract: A data storage element (10) comprises a switch (11) and a ferroelectric capacitor (12). The switch (11) has a control terminal connected to a word line (13), a first current conducting terminal coupled to a bit line (16) via the ferroelectric capacitor (12), and a second current conducting terminal connected to a plate line (14). The data storage element (10) fully restores data in the ferroelectric capacitor (12) after a reading operation without consuming extra power to boost the word line (13) voltage.

Abstract: A phase current reconstruction circuit (10) senses and reconstructs a phase current in a phase bridges (12A). An amplifier (32) in a phase current reconstruction element (22) amplifies a voltage signal across a sensing resistor (18). The amplified voltage signal is transmitted to a sample and hold circuit (34), which reconstructs the phase current in the phase bridge (12A). An over-current comparator (36) compares the amplified voltage signal with a predetermined reference voltage to detect an over-current in the phase bridge(12A). If the over-current in the phase bridge (12A) is detected, an over-current latch (38) interrupts the pulse width modulation signal from a microcontroller (26) to a power switch (16A) in the phase bridge (12A), thereby switching off and protecting the power switch (16A) from damage that may be caused by the over-current.

Abstract: A programmable analog array (10) comprises an array (11) of cells, each cell including analog circuitry (12), a switch control circuit (18), and a digital storage element (16). The switch control circuit (18) receives a clock signal and sequentially configures the circuits within the analog circuitry (12) to realize different circuit functions in accordance with configuration data stored in different digital memory units (17A-17D) within digital storage element (16). During a time interval, the analog signals generated by the analog circuitry (12) before that time interval are stored in an analog storage element (14), which is constructed from a portion of a capacitor network (54) in the analog circuitry (12) and is partitioned into a set of analog memory units (56A-56D). Each analog memory unit (56A-56D) stores the analog signal for a corresponding phase of the clock signal.

Abstract: A protocol between a microprocessor (21) and an interface circuit (11). The interface circuit (11) transmits an enable signal (124) to the microprocessor (21). Upon receiving the enable signal (124), the microprocessor (21) transmits a set of pulses of a window signal (125) to the interface circuit (11), which in turn provides the microprocessor (21) with information concerning a circuit element (36) through a data signal (127). The microprocessor (21) initiates a command by transmitting a pulse of a command signal (126) to the interface circuit (11). The interface circuit (11) accepts and executes the command only if a predetermined chronological condition between the pulse of the command signal (126) and a corresponding pulse of the window signal (125) is satisfied. The microprocessor (21) identifies a malfunctioning interface circuit (11) by timing the enable signal (124) received from the interface circuit (11).

Abstract: An input circuit (10) includes two inverters (12, 16) and an enable transistor (18). When a logic high enable signal is transmitted to a gate electrode of the enable transistor (18). The two inverters (12, 16) form a latch that holds the data at the input port (21) of the input circuit (10). When a logic low enable signal is transmitted to the gate electrode of the enable transistor (18), the latch formed by the two inverters (12, 16) is disabled, thereby allowing fast data transmission through the input circuit (10). When the voltage at the input port (21) is higher than a supply voltage of the input circuit (10), the enable transistor (18) switches off to protect a voltage supply coupled to the input circuit (10).

Abstract: An optoelectric interconnect (70) includes an optical fiber (17) coupled to a ferrule (11) and an optoelectric board (20). Metal layer (14) is disposed over a surface (12) of the ferrule (11). An optoelectric device (61) is coupled to the optoelectric board (20) using tape automated bonding tapes (47, 51). The optoelectric board (20) and the ferrule (11) are positioned adjacent each-other so that optical radiation is transmitted from the optoelectric device (61) to the optical fiber (17). The position of the optoelectric device (61) is adjusted to achieve an optimum position which is characterized by a maximum optical radiation transmitted to the optical fiber(17). Upon achieving the optimum position, two bonding strips (54, 56) are fused with the metal layer (14) on the surface (12) of the ferrule (11).

Abstract: A power source balancing circuit (10) balances two power sources such as two battery cells (12 and 42). When the power source balancing circuit (10) is enabled, it compares a current flowing through the first battery cell (12) and a first resistor (22) with a current flowing through the second battery cell (42) and a second resistor (52). Because the resistance of the first resistor (22) is equal to that of the second resistor (52), a difference between the two currents indicates a difference between the voltages of the two battery cells (12 and 42). If a current difference larger than a predetermined limit is detected, the battery cell (12 or 42) with a higher voltage is discharged through a corresponding discharge resistor (14 or 44) by switching on a corresponding switch (16 or 46). The corresponding switch (16 or 46) is controlled by a corresponding flip-flop (32 or 62).