Abstract: The invention relates to an electronic module comprising a stack of n packages of predetermined thickness E, which are provided on a lower surface with connection balls of predetermined thickness eb, said connection balls being connected to a printed circuit for interconnecting the package. The printed circuit is placed on the lower surface of the package level with the balls, is drilled with metallized holes, in which the balls are located and to which they are connected, and has a thickness eci less than eb so as to obtain a module with a total thickness not exceeding n (E+10% eb).

Abstract: A method for fabricating a re-built wafer which comprises chips having connection pads, comprising: fabricating a first wafer of chips, production on this wafer of a stack of at least one layer of redistribution of the pads of the chips on conductive tracks designed for the interconnection of the chips, this stack being designated the main RDL layer, cutting this wafer in order to obtain individual chips each furnished with their RDL layer, transferring the individual chips with their RDL layer to a sufficiently rigid support to remain flat during the following steps, which support is furnished with an adhesive layer, with the RDL layer on the adhesive layer, depositing a resin in order to encapsulate the chips, polymerizing the resin, removing the rigid support, depositing a single redistribution layer called a mini RDL in order to connect the conductive tracks of the main RDL layer up to interconnection contacts, through apertures made in the adhesive layer, the wafer comprising the polymerized resin, the c

Abstract: The invention relates to a method of interconnecting electronic components of a first wafer (T1) with electronic components of a second wafer (T2), each wafer having metallized vias (1) which pass through the wafer in the thickness direction. The method includes deposition of a drop (3) of conductive ink containing solvents on each via (1) of the first wafer (T1); stacking of the second wafer (T2) on the first so that the vias (1) of the second wafer (T2) are substantially superposed on the vias (1) of the first wafer (T1); removal of 50 to 90% of the solvents contained in the drops (3) by heating or applying a vacuum, so as to obtain a pasty ink; and laser sintering of the pasty ink drops (3) so as to produce electrical connections (31) between the superposed metallized vias (1).

Abstract: A process for fabricating a reconstituted wafer that includes chips having connection pads on a front side side of the chip, this process including positioning of the chips on an adhesive support, front side down on the support; deposition of a resin on the support in order to encapsulate the chips; and curing of the resin. Before deposition of the resin, the process includes bonding, onto the chips, a support wafer for positioning the chips, this support wafer having parts placed on one side of the chips.

Abstract: A process for the wafer-scale fabrication of CMS electronic modules starts from a wafer with metallized outputs, comprising electronic components molded in resin and, on one side, the external outputs of the electronic components on which a nonoxidizable metal or alloy is deposited, and of a printed circuit provided with oxidizable metal or alloy contact pads. In the process, the wafer is cut in predetermined patterns for obtaining reconfigured molded components that include at least one electronic component; the reconfigured components are assembled on the printed circuit, the metallized external outputs of the reconfigured components being placed opposite the metallized contact pads of the printed circuit; and these external outputs are connected solderlessly to the metallized contact pads of the printed circuit by means of a material based on an electrically conductive adhesive or ink.

Abstract: The invention relates to the collective fabrication of n 3D module. It comprises a step of fabricating a batch of n dies i at one and the same thin plane wafer (10) of thickness es comprising silicon, covered on one face with electrical connection pads (20), called test pads, and then with a thin electrically insulating layer (4) of thickness ei, forming the insulating substrate provided with at least one silicon electronic component (11) having connection pads (2) connected to the test pads (20) through the insulating layer.

Abstract: The invention relates to the collective fabrication of n 3D modules. A batch of n wafers I are fabricated on one and the same plate. This step is repeated K times. The K plates are stacked. Plated-through holes are formed in the thickness of the stack. These holes are intended for connecting the slices together. The stack is cut in order to obtain the n 3D modules. The plate 10, which comprises silicon, is covered on one face 11 with an electrically insulating layer forming the insulating substrate. This face has grooves 20 that define n geometrical features, which are provided with an electronic component 1 connected to electrical connection pads 2? placed on said face.

Abstract: The invention relates to a method of interconnecting electronic components of a first wafer (T1) with electronic components of a second wafer (T2), each wafer having metallized vias (1) which pass through the wafer in the thickness direction. The method includes deposition of a drop (3) of conductive ink containing solvents on each via (1) of the first wafer (T1); stacking of the second wafer (T2) on the first so that the vias (1) of the second wafer (T2) are substantially superposed on the vias (1) of the first wafer (T1); removal of 50 to 90% of the solvents contained in the drops (3) by heating or applying a vacuum, so as to obtain a pasty ink; and laser sintering of the pasty ink drops (3) so as to produce electrical connections (31) between the superposed metallized vias (1).

Abstract: A method for interconnecting active and passive components in two or three dimensions, and the resulting thin heterogeneous components. The method comprises: positioning and fixing (11) at least one active component and one passive component on a flat support (23), the terminals being in contact with the support, depositing (12) a polymer layer (24) on all of the support and the components, removing the support (14), redistributing the terminals (15) between the components and/or toward the periphery by metal conductors (26) arranged in a predetermined layout, making it possible to obtain a heterogeneous reconstituted structure, heterogeneously thinning (16) the structure by nonselective surface treatment of the polymer layer and at least one passive component (22).

Abstract: The present invention relates to a process for the vertical interconnection of 3D electronic modules (100), a module comprising a stack of K electronic wafer levels (19) electrically connected together by conductors lying along the direction of the stack, which comprises steps consisting in: A) fabricating a batch of wafer levels (19) comprising n geometric features bounded by dicing lines (14), each feature being provided with at least one electronic component (6) surrounded by insulating resin (9) and connected to electrical connection pads (4), the pads being connected to electrical connection tracks (12) deposited on a dielectric layer (11); each track (12) extends as far as an electrode (13) interconnecting the tracks and located on the dicing lines (14), and comprises a curved segment (12a) defining a zone (15a) that surrounds a location intended to form a via, B) stacking and assembling the K wafer levels (19) so as to superpose said zones (15a); C) drilling vias (15) in the resin (9) plumb with the

Abstract: The invention relates to the collective fabrication of n 3D module. It comprises a step of fabricating a batch of n dies i at one and the same thin plane wafer (10) of thickness es comprising silicon, covered on one face with electrical connection pads (20), called test pads, and then with a thin electrically insulating layer (4) of thickness ei, forming the insulating substrate provided with at least one silicon electronic component (11) having connection pads (2) connected to the test pads (20) through the insulating layer.

Abstract: The present invention relates to an electronic device incorporating a heat distributor. It applies more particularly to devices of the plastic package type, with one or more levels of components. According to the invention, the electronic device, for example of the package type, is provided for its external connection with pads distributed over a connection surface. It includes a thermally conducting plate lying parallel to said connection surface and having a nonuniform structure making it possible, when the device is exposed to a given external temperature, to supply a controlled amount of heat to each external connection pad according to its position on the connection surface. If the device is a package comprising a support of the printed circuit type, the conducting plate will advantageously form an internal layer of said support.

Abstract: The invention relates to a 3D electronic module comprising a stack (100) of at least a first slice (10) and a second slice (30), the first slice (10) having on a face (101) at least one set (4) of electrically conductive protrusions (41), and the second slice (30) comprising at least one zone (61) of electrically insulating material, traversing the thickness of the slice. The second slice (30) comprises at least one electrically conductive element (3) traversing said slice in a zone (61) of electrically insulating material, able to receive a set (4) of protrusions (41) of the first slice (10).

Abstract: The invention relates to the collective fabrication of n 3D modules. It comprises a step of fabricating a batch of n wafers I on one and the same plate, this step being repeated K times, then a step of stacking the K plates, a step of forming plated-through holes in the thickness of the stack, these holes being intended for connecting the slices together, and then a step of cutting the stack in order to obtain the n 3D modules. The plate 10, which comprises silicon, is covered on one face 11 with an electrically insulating layer forming the insulating substrate. This face has grooves 20 that define n geometrical features, which are provided with an electronic component 1 connected to electrical connection pads 2? placed on said face. After the stacking operation, holes are drilled perpendicular to the faces of the plates vertically in line with the grooves. The size of the holes is smaller than that of the grooves so that the silicon of each wafer 10 is isolated from the wall of the hole by resin.

Abstract: The invention relates to an electronic module (100) comprising a stack of n packages (10, 10a, 10b) of predetermined thickness E, which are provided on a lower surface with connection balls (12) of predetermined thickness eb, said connection balls being connected to a printed circuit (20, 20a, 20b) for interconnecting the package. The printed circuit is placed on the lower surface of the package level with the balls, is drilled with metallized holes (23), in which the balls (12) are located and to which they are connected, and has a thickness eci less than eb so as to obtain a module with a total thickness not exceeding n (E+10% eb).

Abstract: The present invention relates to an electronic device incorporating a heat distributor. It applies more particularly to devices of the plastic package type, with one or more levels of components. According to the invention, the electronic device, for example of the package type, is provided for its external connection with pads distributed over a connection surface. It includes a thermally conducting plate lying parallel to said connection surface and having a nonuniform structure making it possible, when the device is exposed to a given external temperature, to supply a controlled amount of heat to each external connection pad according to its position on the connection surface. If the device is a package comprising a support of the printed circuit type, the conducting plate will advantageously form an internal layer of said support.

Abstract: The present invention relates to a method for the thin interconnection of active and passive components in two or three dimensions, and to the resulting thin heterogeneous components. According to the invention, the method comprises: positioning and fixing (11) at least one active component and one passive component on a flat support (23), the terminals being in contact with the support, depositing (12) a polymer layer (24) on all of the support and said components, removing the support (14), redistributing the terminals (15) between the components and/or toward the periphery by means of metal conductors (26) arranged in a predetermined layout, making it possible to obtain a heterogeneous reconstituted structure, heterogeneously thinning (16) said structure by nonselective surface treatment of the polymer layer and at least one passive component (22).

Abstract: The invention relates to a device for interconnecting, in three dimensions, electronic components. In order to decrease the parasitic capacitances between the connections and shielding of the device, metallized grooves are cut in the block of stacked circuits, just clipping the connection to conductors of which are set back from the corresponding face of the block. The assembly is then encapsulated with resin and shielded by metallization. The invention is especially applicable to producing electronic systems in three dimensions with a small size.

Abstract: A method of interconnection in three dimensions and to an electronic device obtained by the method. To increase the compactness of integrated circuit modules, the method stacks and adhesively bonds packages containing a chip connected to output leads by connection conductors inside each package, cuts through the packages near the chips to form a block, the conductors being flush with the faces of the block, and makes the connections on the faces of the block by metalizing and then etching the outlines of the connections. The method also applies to the matching of packages in the replacement of obsolete circuits.