Abstract: Embodiments of the present disclosure provide a display device. The display device includes a backlight module, a first dimming box, a second dimming box, and a liquid crystal display module. The first dimming box is disposed on a light-emitting side of the backlight module. The second dimming box is disposed on a light-emitting side of the first dimming box. The liquid crystal display module is disposed on a light-emitting side of the second dimming box. A color coordinate offset between a color coordinate corresponding to a side viewing angle of 45° under the anti-peep mode and a color coordinate corresponding to a front viewing angle under the anti-peep mode is less than 0.1869.

Abstract: A display panel and a manufacturing method thereof are disclosed. The display panel includes a display device and an anti-reflective layer disposed on the display device. The display device includes a plurality of sub-pixel areas distributed in an array manner. The anti-reflected layer includes a plurality of organic light-transmissive thin films corresponding to the sub-pixel areas. A plurality of inorganic nanoparticles are doped in the organic light-transmissive thin films. The inorganic nanoparticles at a side of the organic light-transmissive thin films away from the display device protrude from a surface of the organic light-transmissive thin films to form a plurality of nano moth-eye structures.

Abstract: The embodiments of the present application provide a method for manufacturing thin-film transistor (TFT) substrate and a TFT substrate thereof. A semi-finished substrate has a first region, a second region, and a third region. The semiconductor layer and the insulating layer of the semi-finished substrate are patterned under the shielding of the first etching barrier layer and the second etching barrier layer having different thickness, so that only the semiconductor layer in the second region is kept and causing the thickness of the insulating layer in the first region is greater than the thickness of the insulating layer in the third region.

Abstract: A display panel includes a first display area. The first display area includes a display substrate and an optical layer. The display substrate includes a pixel defining layer and a cathode layer disposed on the pixel defining layer. The pixel defining layer includes a plurality of pixel openings and a plurality of supporting portions each disposed between two adjacent pixel openings. A thickness of a part of the cathode layer on each of the pixel opening is greater than a thickness of a part of the cathode layer on each of the supporting portions. The optical layer is disposed on the cathode layer and includes a plurality of first optical structures corresponding to the supporting portions. Each of the first optical structures includes a first surface close to the cathode layer, a second surface opposite to the first surface, and a side surface that is a total reflective surface.

Abstract: The present disclosure provides a method for determining a pixel voltage, an electronic device, and a storage medium. The method includes: obtaining an initial color shift ratio of a sub pixel to be tested, obtaining an initial evaluation value of a preset grayscale value, and obtaining a current evaluation value of the preset grayscale value according to a current color shift ratio; comparing the initial evaluation value with the current evaluation value; and determining a standard sub pixel voltage of the sub pixel to be test according to the current color shift ratio, when the current evaluation value is greater than the initial evaluation value.

Abstract: The present application provides a display panel and a display device, the display panel includes a first display area and a second display area, wherein a light emitting layer of the display panel includes a plurality of first pixels disposed in the first display area and a plurality of second pixels disposed in the second display area, and in the first display area, a first opening is provided between a second electrode layer and adjacent first pixels, so as to improve a light transmittance of the first display area, and alleviate a problem of a poor light transmittance of a display screen in which a conventional under-screen camera technology is applied.

Abstract: The present application discloses a display device, the display device includes: a display panel and a printed circuit board. A first bonding region is disposed on the display panel. The first bonding region includes a first bonding terminal. A second bonding region is disposed on the printed circuit board. The second bonding region includes a second bonding terminal. The first bonding terminal is connected to and contacts the second bonding terminal. The display device provided by the present application can reduce a width of a frame of the display device and improve a screen ratio of the display device.

Abstract: A luminance compensation circuit includes: a light-emitting circuit; a luminance detector electrically connected to a first power terminal, a second power terminal, and a first node; a reading device electrically connected to the first node; and a timing controller electrically connected to the reading device and the light-emitting circuit.

Abstract: The present disclosure provides a gate driver on array (GOA) circuit including a plurality of GOA units disposed in N-stage cascade, and an nth-stage GOA unit includes a node control module, a pull-up module, a pull-down module, a pull-down maintaining module, and a stop control module, wherein 1<n<N?1, and both the n and the N are positive integers.

Abstract: A display screen splicing method and a spliced display screen are provided. According to the display screen splicing method provided in the embodiments of the present disclosure, a first to-be-spliced panel is connected to a second to-be-spliced panel in a splicing area using conductive connecting portions. In addition, the conductive connecting portions are manufactured by inkjet printing to perform connection between the two adjacent to-be-spliced panels by using signals, so as to realize narrow-seam splicing. By means of the display screen splicing method provided in the embodiments of the present disclosure, the process is simplified, and the precision requirements for devices are reduced.

Abstract: Gate driving circuits, display panels, and display devices are provided. The gate driving circuit includes cascaded gate driving units, each of which includes an input unit, an output unit, a reset control unit, and a pull-down holding unit. The input unit outputs a driving signal to a first node. The output unit outputs a scanning signal in response to the driving signal. The reset control unit outputs a reset control signal to a second node during a first period. The pull-down holding unit receives the reset control signal. The pull-down holding unit outputs a first voltage signal to the first node in response to the reset control signal to reset a potential of the first node during the first period, and outputs the first voltage signal to the first node to maintain the potential of the first node during a second period.

Abstract: A gate drive circuit and a display panel. The gate drive circuit includes one or more shift register groups. Each of the shift register groups includes N shift adjacent registers that output in sequence, with N being an integer greater than or equal to 3. Each of the shift registers includes a first output stage and a frequency division control module. The first output stage is configured to output a gate drive signal. The frequency division control module is configured to control outputting of the gate drive signal based on a refresh frequency. A control end of each frequency division control module in each of the shift register groups receives a control signal with a different phase and a same frequency, respectively, to adjust a pulse width of the gate drive signal and maintain a same pulse width at different refresh frequencies.

Abstract: An embodiment of the present application discloses an array substrate and a liquid crystal display panel. The array substrate uses a first barrier layer including a first aperture in an aperture region. The first barrier layer is at least correspondingly disposed in a thin film transistor disposing region and a gate driver on array circuit region. The first barrier layer is configured to block the alkaline cation from spreading along a direction to the active layer. Along a direction at a right angle from the substrate to the active layer, a depth by which the alkaline cation enters the first barrier layer is less than or equal to 20 ?.

Abstract: A micro light-emitting diode display panel and a micro light-emitting diode display device. A prism layer is provided with a void, which surrounds a light-emitting chip and is arranged axially symmetrically with respect to a center line of the light-emitting chip. Therefore, a distance between the light-emitting chip and the void in a transverse direction is equal to a distance between the light-emitting chip and the void in an oblique direction, and an angle at which a light ray emitted from the light-emitting chip is reflected at a contact surface between the prism layer and the void in the transverse direction is same as an angle at which a light ray emitted from the light-emitting chip is reflected at the contact surface in the oblique direction. Accordingly, a plane formed by the light-emitting chip and the contact surface is same as a tangential focal plane or a sagittal focal plane.

Abstract: The present application discloses a display panel including a quantity N of driver units that are cascaded. The quantity N of the driver units are arranged along a first direction. Each of the driver units includes a first output module, a signal generation module, and a second output module disposed along a second direction. The first output module is configured to output a first gate electrode driving signal. The second output module is configured to output a second gate electrode driving signal. The first gate electrode driving signal is different from the second gate electrode driving signal. The first output module includes a first buffer unit and a second buffer unit stacked on each other along a third direction. The present application stacks two buffer units in the first output module, which reduce a width of a frame occupied by the first output module while guaranteeing performance of transistors.

Abstract: A display panel is provided. The display panel includes an array substrate, a first electrode layer and a pixel definition layer. The first electrode layer includes a pixel electrode layer and an auxiliary electrode layer. The pixel definition layer includes a first opening and a second opening. The first opening is disposed in correspondence with the pixel electrode layer, and the second opening is disposed in correspondence with the auxiliary electrode layer. A side surface of the pixel electrode layer away from the array substrate is lower than a side surface of the auxiliary electrode layer away from the array substrate.

Abstract: The embodiment of the present application discloses a liquid crystal display panel, the liquid crystal display panel includes a first substrate and a second substrate disposed opposite to each other. A frame sealant and a boss contacting each other are disposed in a frame sealant region, and the frame sealant at least partially overlaps the boss in a film thickness direction. A boss cooperating with the frame sealant to perform a sealing function is disposed in the frame sealant region. The boss reduces a volume of the frame sealant and lowers a time required for curing the frame sealant to improve a productivity.

Abstract: An array substrate and a display panel are provided. The array substrate includes a substrate, and at least three pixel unit. The pixel unit includes at least one pixel group and at least three data line groups disposed on the substrate. Each pixel group includes six sub-pixels arranged at intervals in a first direction. Each sub-pixel includes at least one pixel electrode. The at least three data line groups include three data line groups. Each data line group corresponds to a pixel electrode of one sub-pixel. The data line group is located on one side of the pixel electrode which is adjacent to the substrate. Each data line group includes two data lines arranged at intervals in the first direction. The pixel electrode of each sub-pixel is electrically connected to one data line.

Abstract: Embodiments of the present disclosure provide a display panel and a display terminal. The display panel includes at least one ultraviolet sensing transistor and at least one control transistor disposed on a substrate, and a color film substrate including a light blocking unit; wherein the ultraviolet sensing transistor includes an ultraviolet absorbing layer, and an orthographic projection of the light blocking unit on the substrate covers an orthographic projection of the ultraviolet absorbing layer on the substrate. According to the embodiment of the present disclosure, the light blocking unit absorbs or blocks the visible lights to prevent the visible lights from entering into the ultraviolet absorbing layer.