Abstract: A microstrip collinear array includes a bearing member, two first antenna assemblies, two second antenna assemblies, a first connecting line, and a second connecting line. The two first antenna assemblies are juxtaposed on the bearing member. Each of the first antenna assemblies includes several first planar antennas. The two second antenna assemblies are juxtaposed on the bearing member and are respectively and correspondingly located on an opposite side of the two first antenna assemblies. Each of the second antenna assemblies includes several second planar antennas. The first connecting line and the second connecting line are disposed on the bearing member. The second connecting line is located on an opposite side of the first connecting line and is electrically connected to the first connecting line. The first connecting line is electrically connected to the first antenna assemblies. The second connecting line is electrically connected to the second antenna assemblies.

Abstract: An antenna pattern control system includes a wireless access point, a memory and a processor. The wireless access point includes a plurality of adjustable antennas. Different operative arrangements of the adjustable antennas correspond to a plurality of antenna pattern combinations. The memory stores a plurality of real-time indicators recorded when the adjustable antennas are operating according to these antenna pattern permutations. The processor selects candidate pattern permutations from the antenna pattern permutations according to a cluster distribution of one of the real-time indicators located in a coordinate system. The processor also selects a target pattern permutation from the candidate pattern permutations according to a cluster distribution of at least two of the other real-time indicators. The processor outputs the target pattern permutation to the wireless access point in order to control the adjustable antennas of the wireless access point according to the selected target pattern permutation.

Abstract: An electronic device includes a case engaged with a cable fixing device. The cable fixing device includes at least one first restricting portion and a fixing frame which are connected to the case. The fixing frame could be moved relative to the case between a first position and a second position. The fixing frame has at least one hollow portion for being passed through by a cable and at least one second restricting portion disposed on a peripheral edge of the hollow portion. When the fixing frame is located in the first position, the second restricting portion is away from the first restricting portion. When the fixing frame is located in the second position, the second restricting portion is closer to the first restricting portion than the fixing frame located in the first position. The second restricting portion and first restricting portion jointly restrict a position of the cable.

Abstract: A burn-in chamber is provided, configured to provide the required temperature for a device under test (DUT), including a side wall, a guiding plate, an air flow plate, a partition assembly, and a fan. The air flow plate has a ventilation structure, and the guiding plate is located between the side wall and the air flow plate. The partition assembly is disposed on both sides of the air flow plate. The partition assembly and the air flow plate together form an accommodating space for accommodating the DUT. The partition assembly forms a return channel with respect to the other side of the accommodating space with the side wall. When the fan is active, air from the accommodating space passes through the air flow plate and is guided to the return channel via the guiding plate, and air is returned to the accommodating space through the return channel.

Abstract: The present disclosure provides an antenna array system that includes a plurality of antenna array units and a processor. The antenna array units are evenly arranged in different orientations, where each antenna array unit comprises a plurality of antenna elements with different azimuth angles, and the different azimuth angles of the antenna elements in the each antenna array unit form a vector, where the vectors corresponding to the antenna array units constitute a vector matrix that matches a predetermined rule. The processor is electrically connected to the antenna array units.

Abstract: A network device supporting TRILL protocol includes a memory, a processor, and a communication interface. The memory includes a lookup table stored therein. The processor is coupled to the memory. The communication interface is coupled to the processor. The communication interface includes a trunk port and an access port and is configured to receive a first packet. When the processor determines that an output port corresponding to a destination address of the first packet is the trunk port, and determines that there is a lack of nickname information corresponding to the destination address according to the look up table, a second packet is transmitted through the trunk port of the communication interface. The second packet includes an enable local bit. The second packet and the first packet include the same payload information.

Abstract: A waterproof assembly includes a casing, a gasket, and a cap. The casing has an opening. The gasket includes a main body and a protruding portion. The main body has a first circular raised structure configured to abut against an inner surface of the casing. The protruding portion is connected to the main body and is configured to at least partially protrude out of the casing through the opening. The cap is configured to abut against a side of the main body away from the opening. The cap has a through hole configured to be aligned with the protruding portion. The casing further has a plurality of fixing members configured to abut against a side of the cap away from the gasket.

Abstract: A cord retainer is configured to be detachably disposed on an electronic device. The cord retainer includes a hook portion, a connection portion, and a clamp portion. The hook portion is configured to be fastened to the handle of the electronic device. The hook portion may be a tubular structure that extends along an extension direction. The connection portion is connected to the hook portion. The clamp portion is connected to the connection portion, and is configured to retain a cord attached on the electronic device. The clamp portion may be a plate structure that extends along an extension plane that is parallel to the extension direction.

Abstract: A planar antenna module includes a plurality of planar antennas, a first transmission line electrically connected to the planar antennas, and at least one gain enhancement structure formed on the first transmission line. Each gain enhancement structure has a plurality of toothed portions spaced apart. With the design of the gain enhancement structure, the gain of the planar antenna module could be enhanced.

Abstract: A cord retainer is configured to be detachably disposed on an electronic device. The cord retainer includes a hook portion, a connection portion, and a clamp portion. The hook portion is configured to be fastened to the handle of the electronic device. The hook portion may be a tubular structure that extends along an extension direction. The connection portion is connected to the hook portion. The clamp portion is connected to the connection portion, and is configured to retain a cord attached on the electronic device. The clamp portion may be a plate structure that extends along an extension plane that is parallel to the extension direction.

Abstract: A network interface card installed in a chassis switch, which includes a switch device and a controller, is provided. The switch device includes a plurality of ports coupled to other network interface cards in the chassis switch, and each of the other network interface cards is a fabric card or a line card. The controller is configured to perform different acts according to the card type of the network interface card, wherein the acts constitute a specific process of path planning which may prevent loops from occurring in the communication paths of control packet delivery between multiple network interface cards in the chassis switch.

Abstract: An antenna module is disclosed. The antenna module includes a circuit board and at least one antenna set. Wherein, the antenna set includes a driving antenna and a plurality of parasitic antennas. The driving antenna is formed on the circuit board, and the parasitic antennas are positioned with the driving antenna as a center on the circuit board. Whereby, the space occupied by the antenna module can be small, and beams of wireless signals radiated by the antenna module can be controlled.

Abstract: A communication method includes grouping a plurality of antenna patterns of a communication device according to an antenna device group corresponding to different antenna combinations to form a plurality of antenna pattern groups, and selecting an antenna pattern group from the antenna pattern groups; according to a plurality of signal parameter statistics of a plurality of antenna pattern combinations corresponding to each of the selected antenna pattern group, selecting a first antenna pattern combination and a last antenna pattern combination among the plurality of antenna pattern combinations; and according to first data related to the first antenna pattern combination and second data related to the last antenna pattern combination, setting the first antenna pattern combination or the last antenna pattern combination as a transmission antenna pattern combination for data transmission.

Abstract: An A-MSDU sub-frame processing method is provided. The method includes: allocating a first sub-block and a second sub-block adjacent to the first sub-block in a memory when an Ethernet frame is received, wherein the first sub-block includes a block with a preset bit length, the second sub-block includes a block with a bit length corresponding to the Ethernet frame, and a pointer initially points to a first initial address in the second sub-block; sequentially storing header information of the Ethernet frame into the second sub-block according to a header format of the Ethernet frame; filling the first sub-block with length information of the Ethernet frame; shifting the pointer along a first direction to a second initial address whose distance shifted from the first initial address is the preset bit length; and reading out data in a length along a second direction from the second initial address to generate the A-MSDU sub-frame.

Abstract: The inventive subject matter discloses a handle, a pluggable module, and an electronic apparatus. The electronic apparatus includes a frame body and a plurality of pluggable modules. Each of the pluggable modules includes a rack and a handle, wherein the rack is adapted to receive an electronic module. The handle includes two elastic arms and a force-bearing arm, wherein each of the two elastic arms includes a hook section, and the two hook sections are adapted to be engaged with positioning structures of the frame body respectively. The force-bearing arm is connected between the two elastic arms, and the two elastic arms shift toward each other to enable the two hook sections to be detached from the positioning structures when a force is applied to the force-bearing arm. With the aforementioned design, the pluggable module could be instinctively inserted into or removed from the electronic apparatus.

Abstract: The present invention discloses an antenna tuning system and method thereof. The method comprises the following steps: choosing a parasitic antenna that combined with a main antenna, the strongest received signal strength indicator of a target station is detected; controlling the selected parasitic antenna that combined with a main antenna, to generate a scattering resonance through turning on or off a switch unit; and controlling a diffraction radiation pattern between the main antenna and the selected parasitic antenna through adjusting a load of a designed circuit.

Abstract: A chassis switch including a network interface card is provided. The network interface card includes a first Virtual Local Area Network (VLAN) ID to a first packet originating from an internal Internet Protocol (IP) address, to prevent the first packet from being forwarded to the outside of the chassis switch. In addition, the network interface card further includes a second VLAN ID to a second packet originating from an external IP address, to allow the second packet to be forwarded to the outside of the chassis switch.

Abstract: A chassis switch including a network interface card is provided. The network interface card includes a first Virtual Local Area Network (VLAN) ID to a first packet originating from an internal Internet Protocol (IP) address, to prevent the first packet from being forwarded to the outside of the chassis switch. In addition, the network interface card further includes a second VLAN ID to a second packet originating from an external IP address, to allow the second packet to be forwarded to the outside of the chassis switch.

Abstract: An A-MSDU sub-frame processing method is provided. The method includes: allocating a first sub-block and a second sub-block adjacent to the first sub-block in a memory when an Ethernet frame is received, wherein the first sub-block includes a block with a preset bit length, the second sub-block includes a block with a bit length corresponding to the Ethernet frame, and a pointer initially points to a first initial address in the second sub-block; sequentially storing header information of the Ethernet frame into the second sub-block according to a header format of the Ethernet frame; filling the first sub-block with length information of the Ethernet frame; shifting the pointer along a first direction to a second initial address whose distance shifted from the first initial address is the preset bit length; and reading out data in a length along a second direction from the second initial address to generate the A-MSDU sub-frame.

Abstract: A PCI Express network card is disclosed, including a circuit board, a plate, a plurality of integrated circuits, and two heat sinks. The circuit board has five ports. The plate is provided on the circuit board and near a front edge of the circuit board, wherein the plate has a plurality of openings. The integrated circuits are provided on the circuit board, including a first processor and a second processor, which consume the most power. The first processor and the second processor are arranged in a staggered way. Each of the heat sinks abuts against the first processor and the second processor, respectively. An area of each of the heat sinks is greater than an area of each one of the first processor and the second processor. Whereby, effective heat dissipation could be achieved.