Abstract: An encoding/decoding system in an optical disk storage device for performing compact disc/digital video disk (CD/DVD) encoding/decoding of data. The encoding/decoding system includes address mappers for C1, C2, CD P/Q, and DVD inner/outer codes respectively and a shareable Reel-Solomon (RS) encoder/decoder. The shareable RS encoder/decoder is capable of selectively being coupled to either one of the address mappers. When the encoding/decoding system is encoding, the shareable RS encoder/decoder employs a generation polynomial of RS code to generate a parity code of 2T symbols and output a codeword of N symbols, wherein the values of N and 2T are associated with the selected address mapper.

Abstract: A memory mapping method for mapping a data array into a memory. The memory mapping method provides the two-directional access in the data array. The memory mapping method first equally divides each row of the data array into some basic units based on the number of the columns of the data array. Next, a predetermined number of adjacent basic units in the same column are arranged into a basic memory block. Finally, the basic memory blocks are mapped into the memory.

Abstract: A Viterbi detector for use in a partial response maximum likelihood (PRML) signal processing apparatus. The Viterbi detector can be used for different partial response (PR) equalizations with different parameters, and can be used for different PRML signal processing apparatuses such as high speed optical disk systems. The Viterbi detector includes an input buffer, a branch metric calculation unit, an add-compare-select circuit, a path memory unit, and a clock buffer. The Viterbi is designed based on a union trellis diagram relation obtained by combining trellis diagram relations associated with the PR equalizations with the parameters. According to the invention, the Viterbi detector has advantages of saving hardware space and conveniently changing PR equalizations with different parameters.

Abstract: A control system and method for controlling a sled of an optical storage device by using a stepping motor. The optical storage device includes a pick-up head having a lens and a sled. The control system includes a tracking actuator's controller used to receive a tracking signal TE for generating a tracking control signal TRO to control positions of the lens; a numerical controller connected with the tracking actuator's controller used to receive the tracking control signal TRO for generating a numerical control signal; a frequency converter connected with the numerical controller used to receive the numerical control signal for generating a pulse flag signal and a direction flag signal; and a ring generator connected with the frequency converter used to receive the pulse and direction flag signal for producing a sled control signal to drive the stepping motor for controlling the sled.

Abstract: The present invention provides a decoding system and method for an optical disk storage device to receive and decode the data of the disk. The present invention does not need to increase the clock frequency and the bus width of the decoding system, it can effectively decrease the access times to the data buffer and the system response time by changing the structure of the conventional decoding system, in this way the present invention increases the parallel processing capability and the decoding speed of the system, thus, it can enhance the entire device to become a high speed optical storage device.

Abstract: The present invention provides a decoding system and method for an optical disk for receiving and decoding data from the disk. The present invention does not need to increase the clock frequency and the bus width of the decoding system, it can effectively decrease the access times to the data buffer and the system response time by changing the structure of the conventional decoding system, in this way the present invention increases the parallel process capability and the speed of the decoding, thus, it can become a high speed DVD.

Abstract: A method and system for optical disk decoding, which is used for decoding an error correction code (ECC) block. The method and system can determine whether it is to perform the outer code decoding or the inner code decoding first. In addition, during the inner code decoding, the EDC checking is performed. After the inner code decoding or the outer code decoding, it is determined whether one of the following is true: (1) the error correction of the ECC block is complete; (2) the number of errors is over the limitation of error correction so that the error-correcting operation cannot be performed; or (3) the decoding operations are performed for a number of times but the correction is not complete. If one of the conditions is true, the inner code decoding or the outer code decoding is terminated. Next, the descrambling and the EDC checking are performed. Being passed in the EDC checking, the data are sent to a host; otherwise, re-transmission of the corresponding data for processing is required.

Abstract: The system and method is used for CAV (Constant Angular Velocity) control format recording, whereas the existing disk data is recorded under CLV (Constant Linear Velocity) control format recording. When the PUH receives a laser driver signal, it generates a feed signal and a wobble signal. The feed signal is received by the automatic power control; thereafter the automatic power control generates a first control signal used for causing the laser driver to adjust the laser driver signal. After the ATIP decoder receives the wobble signal, the ATIP decoder generates and outputs ATIP decoded data to the CLV value detector. The CLV value detector receives ATIP decoded data and generates a CLV decoded data to the laser power control. The laser power control receives the CLV decoded data and generates a second control signal used for causing the automatic power control to adjust the first control signal.

Abstract: A package of a semiconductor chip with array-type bonding pads. The semiconductor chip has a plurality of bonding pads located about periphery of the chip, in which the semiconductor chip is characterized at the bonding pads being positioned in at least four rows along each side of the chip, the four rows comprising an inner row, a mid-inner row, a mid-outer row, and an outer row. The inner row and the mid-inner row of the bonding pads consist of signal pads, and the outer row and the mid-outer row of the bonding pads consist of power pads and ground pads.

Abstract: A computer system for multi-type DRAM support includes a first slot for receiving a first type DRAM, a second slot for receiving a second type DRAM, a north bridge chip, and a control circuit. The first slot includes a plurality of first slot pins, and each of them corresponds to a first pin assignment. The second slot includes a plurality of second slot pins, and each of them corresponds to a second pin assignment. The north bridge chip includes a plurality of chip pins, and each of them corresponds to a first and second pin assignment. When the control circuit generates a first control signal, the pin assignments of the chip pins are defined as the first pin assignments. When the control circuit generates a second control signal, the pin assignments of the chip pins are defined as the second pin assignments.

Abstract: A Viterbi detector for extending tolerable extent of DC bias is disclosed. By adding a fixed value to a reference level or subtracting a fixed value from the reference level, the tolerable extent of the DC bias of the input signal is increased. According to the invention, this effect can be achieved with a control circuit and the tolerable extent of the DC bias can be increased by about 100% as compared with the tolerable extent of the DC bias in the conventional approaches.

Abstract: A computer motherboard selectively uses various memories in the light of a dummy card. The computer motherboard comprises a serial resistor, and a first slot and a second slot for holding various memories, respectively. Various memories can be configured on the motherboard without additional settings by means of predefined dummy card or/and rearranging the location of the serial resistor.

Abstract: A portable peripheral apparatus with an embedded storage module. The apparatus is connected to a computer via a communication interface, such as a USB interface or an IEEE 1394 interface. The portable peripheral apparatus includes a main device and an embedded storage module. The embedded storage module connects to the computer via the communication interface and has a storage device. The storage device stores peripheral data. If the storage device is a rewritable memory, then when receiving a specific instruction from the computer, the embedded storage module receives and updates the peripheral data stored in the storage device.

Abstract: The long seek control system and method include a reference velocity mapping unit that obtains a reference velocity when the dual actuator is moved by the residual track count; a velocity estimator for outputting an estimated velocity and obtaining a sled control effort by subtracting the estimated velocity from the reference velocity; and an electrical damper for receiving the sled control effort and simultaneously receiving the displacement of the dual actuator to output a damping control effort to the fine actuator, and reduce the vibration of the fine actuator during the long seek operation. In the reference velocity mapping unit, a reference velocity curve is used to describe the mapping relation between the residual track count and the reference velocity. The reference velocity curve includes a linear part and several quadratic parts with different quadratic functions.

Abstract: An integrated capacitor includes a semiconductor substrate. A first vertical plate is laid over the semiconductor substrate. The first vertical plate consists of a plurality of first conductive slabs connected vertically using multiple first via plugs. A second vertical plate is laid over the semiconductor substrate in parallel with the first vertical plate. The second vertical plate consists of a plurality of second conductive slabs connected vertically using multiple second via plugs. A conductive plate is laid under the first vertical plate and second vertical plate over the semiconductor substrate for shielding the first vertical plate from producing a plate-to-substrate parasitic capacitance thereof. The second vertical plate is electrically connected with the conductive plate using a third via plug.

Abstract: A method of controlling an optical drive to perform a braking process in a layer jump process. The optical drive has a vertically movable pickup head, a preamplifier, a controller, and a low pass filter. The controller receives a focus error signal produced by the preamplifier to produce a focus control signal, and sends the focus control signal to the low pass filter to produce a layer distance balancing signal, so that the pickup head is controlled by the layer distance balancing signal to perform the layer jump process. The method of the present invention comprises the steps of: performing the braking process in accordance with a braking signal and the layer distance balancing signal when the focus error signal reaches a braking start point; and performing a closed-loop focusing control process when the focus error signal reaches a closed-loop focusing control point.

Abstract: A package of a semiconductor chip with array-type bonding pads. The semiconductor chip has a plurality of bonding pads located about periphery of the chip, in which the semiconductor chip is characterized at the bonding pads being positioned in at least four rows along each side of the chip, the four rows comprising an inner row, a mid-inner row, a mid-outer row, and an outer row. The inner row and the mid-inner row of the bonding pads consist of signal pads, and the outer row and the mid-outer row of the bonding pads consist of power pads and ground pads.

Abstract: The present invention discloses an apparatus for controlling a layer jump process of an optical drive. The layer jump control apparatus has a pick up head having a lens and a voice coil motor, a preamplifier for producing a focusing error signal, a controller for receiving the focusing error signal and producing a focusing control signal, a low pass filter for receiving the focusing control signal and producing a layer distance balancing signal, and a driving device to send a driving force to the pick up head.

Abstract: A read channel apparatus is disclosed for reading data recorded on an optical storage system at a predetermined baud rate. The apparatus asynchronously samples an analog read signal generating from the optical storage system and subtracts an estimated DC offset from the asynchronous sample values to generate a sequence of asynchronous DC-removed sample values. The asynchronous DC-removed sample values are separately interpolated by two interpolators to generate a sequence of synchronous even-time sample values and a sequence of synchronous odd-time sample values respectively. The synchronous even-time and odd-time sample values are separately equalized by two equalizers in accordance with a target spectrum to generate a sequence of even-time equalized sample values and a sequence of odd-time equalized sample values respectively. A DC offset estimator generates the estimated DC offset from the even-time equalized sample values and the odd-time equalized sample values.

Abstract: A data processing system and a method for accessing data therein. The data processing system includes a microprocessor, an application specific integrated circuit (ASIC), and a memory. The ASIC is coupled between the microprocessor and the memory and is utilized to communicate with an external computer system for downloading a program code from the external computer system to the memory in which the program code is stored in a memory region of the memory through the ASIC. In addition, the ASIC is for mapping the memory region onto an external memory address space of the microprocessor. The microprocessor generates an address latch enable (ALEN) signal, program memory enable (PMEN) signal, read enable (RDEN) signal, write enable (WREN) signal, and a first address signal.