Abstract: Techniques for improving overall data throughput in a computer system, especially during the playing of movies from CD-ROMs provides for a direct flow of data between the CD-ROM and the MPEG card, greatly reducing system memory usage and bus utilization. Control circuitry is responsive to signals from the CPU, which signals specify whether data from the CD-ROM can be sent directly to the MPEG decoder circuit or needs to be sent over the buses to the system memory. Accordingly, different transmission paths are used, depending on the attribute and destination of the data in order to reduce unnecessary data flow in the system and unnecessary consumption of system resources.

Abstract: The present invention provides an error correction method that is used in full response read channels. This method includes the steps of: obtaining a read signal from a storage medium and converting the read signal into channel bits that are recorded in the storage medium, such as a DVD disk, in the NRZI format; and using the Viterbi detector to determine whether bit state transitions in the channel bits occur within a predetermined run-lengths of the RLL codes. If transitions occur within the predetermined run-lengths, then the values of the bits with state transitions are corrected.

Abstract: A control system and method for controlling a sled of an optical storage device by using a stepping motor. The optical storage device includes a pick-up head having a lens and a sled. The control system includes a tracking actuator's controller used to receive a tracking signal TE for generating a tracking control signal TRO to control positions of the lens; a numerical controller connected with the tracking actuator's controller used to receive the tracking control signal TRO for generating a numerical control signal; a frequency converter connected with the numerical controller used to receive the numerical control signal for generating a pulse flag signal and a direction flag signal; and a ring generator connected with the frequency converter used to receive the pulse and direction flag signal for producing a sled control signal to drive the stepping motor for controlling the sled.

Abstract: A computer system for multi-type DRAM support includes a first slot for receiving a first type DRAM, a second slot for receiving a second type DRAM, a north bridge chip, and a control circuit. The first slot includes a plurality of first slot pins, and each of them corresponds to a first pin assignment. The second slot includes a plurality of second slot pins, and each of them corresponds to a second pin assignment. The north bridge chip includes a plurality of chip pins, and each of them corresponds to a first and second pin assignment. When the control circuit generates a first control signal, the pin assignments of the chip pins are defined as the first pin assignments. When the control circuit generates a second control signal, the pin assignments of the chip pins are defined as the second pin assignments.

Abstract: Improved down mixing of audio channels of compressed digital audio signals by down mixing in the frequency domain. Fast virtual transform is applied to transform short DCT coefficients into long DCT coefficients, and down mixing is performed on the long DCT coefficients. Inverse discrete cosine transform is performed on the down mixed set of long DCT coefficients, generating signals in the windowing domain. The windowing domain signals are then overlapped and added to generate time domain signals suitable for further amplification. Down mixing in the frequency domain reduces the number of computations required.

Abstract: This invention discloses a novel design to solve the clock skew problems in a data processing system by using PLL circuitry inside a memory controller in combination with an adjustable delay element to provide a write clock signal, a read clock signal, and a memory clock signal for triggering the write data buffer and the read buffer of the memory controller, and the memory module respectively. The memory clock signal has a phase lead relative to the read clock signal and a phase lag relative to the write clock signal. The phase lead and the phase lag compensate for phase differences between clock signals arriving at the read data buffer and the write data buffer of the memory controller, and the memory module respectively due to phase delays resulting from the different paths for transmitting clock signals, thereby synchronizing the clock signals.