Abstract: An access network adapted to be coupled to a local exchange over a high-speed link is provided. The access network has a digital line carrier having a port adapted to be coupled to the high-speed link and a plurality of line cards. Each line card has at least one port adapted to be coupled to a transceiver. The digital line carrier selectively connects a transceiver associated with a port of one of the plurality of line cards of the digital line carrier with a transceiver associated with a port of another line card of the digital line carrier based on a signal sent to and returned by the local exchange.

Abstract: A digital to analog converter is provided. The converter includes a multi-bit counter, a first and a second plurality of logic gates coupled to the multi-bit counter, a digital input selectively coupled to the first and second plurality of logic gates. . The converter further includes a first AND gate coupled to an output of the first plurality of logic gates and a second AND gate coupled to an output of the second plurality of logic gates. In addition, the converter includes a clock coupled to an input of the first and second AND gates and an input of the multi-bit counter and a filter coupled to an output of the first and second AND gates, wherein the filter includes an output for an analog signal based on the digital input.

Abstract: A digital to analog converter is provided. The converter includes a multi-bit counter, a first and a second plurality of logic gates coupled to the multi-bit counter, a digital input selectively coupled to the first and second plurality of logic gates. The converter further includes a first AND gate coupled to an output of the first plurality of logic gates and a second AND gate coupled to an output of the second plurality of logic gates. In addition, the converter includes a clock coupled to an input of the first and second AND gates and an input of the multi-bit counter and a filter coupled to an output of the first and second AND gates, wherein the filter includes an output for an analog signal based on the digital input.

Abstract: An electronic system is provided. The electronic system includes a logic device and at least one input/output interface coupled to the logic device. The electronic system further includes an input/output (I/O) device with memory coupled to the at least one input/output interface, wherein the memory of the I/O device is mapped as an address space region that is directly readable and writable by a processor.

Abstract: There are disclosed methods and apparatus for testing memory components for faults, defects or the like, by generating a testing sequence that produces various bit combinations as well as current changes, that when coupled, stresses or fatigues the memory component, and allows for the evaluation of single bits. The testing sequence is provided in cycles, formed of complement word pairs of N bit words. The first, or initial, cycle typically includes a first word of all binary zeros. Successive or subsequent cycles include a shifted bit in each subsequent first word. The testing pattern is written into the memory component(s) under test and corresponding words are read from the memory component(s). The written and read words are then compared, with this comparison analyzed for detection of faults, defects or the like in the memory component(s).

Abstract: A method of ring protection is provided. The method includes feeding traffic on two transmission rings at a head end node and summing all traffic received on the transmission rings at the head end node. When a facility failure is detected, by a remote node, on one of the two transmission rings, transmitting forward alarm signals on the one transmission ring and return alarm signals on the other transmission ring and globally selecting the one transmission ring to transmit traffic and the other transmission ring to receive traffic from the head end node. When a remote node receives a forward alarm signal, the remote node passes the forward alarm signal on the transmission ring on which the forward alarm signal was received and globally selects the transmission ring on which the forward alarm signal was received to transmit traffic and the other transmission ring to receive traffic from the head end node.

Abstract: A linked list buffer circuit can be configured to store different linked lists. The buffer includes insert logic and an insert state machine to add ATM cells to the linked lists in the buffer. Extract logic and an extract state machine allow for the removal of ATM cells from the linked lists in the buffer. Because, ATM cells can have different levels of priority, programmable monitor circuitry is provided to monitor the linked lists in the buffer. The monitor circuitry keeps track of buffer and list capacity, and also keeps track of cell loss priority and delay priority cells of the buffer and the linked lists. This information is used to drop received cells if necessary. The linked list monitor circuitry can be configured based upon the linked list configuration of the buffer. The linked list monitor can be configured by changing threshold levels provided to counter/comparator circuitry. Assignments of internal counter circuitry are also programmable based upon the buffer configuration.