Abstract: A forward error correction system comprises a forward error correction (FEC) module and a transmission module. The FEC module is configured to define a plurality of FEC code words, and the transmission module is configured to transmit the FEC code words to a remote receiving unit via a plurality of communication connections. The transmission module is further configured to ensure that characters of each of the FEC code words are transmitted across different ones of the communication connections.

Abstract: A byte boundary information recovery mechanism locates the first bits of respective bytes of an asynchronous transfer mode (ATM)-based serial data stream, used by a frame synchronization mechanism to delineate respective cells of the ATM stream, and thereby enables transceiver equipment to successfully receive and parse ATM traffic. The invention employs a counter offset-based scheme that generates an output signal in potential alignment with the (first bit) boundary of a byte of the data stream, in response to the contents of a counter reaching a prescribed count value. It then iteratively shifts, as necessary, the bit time at which the output signal is produced relative to the counting operation of the counter, until the output signal is aligned with the boundary of a byte of the data stream.

Abstract: A (DS3) network interface unit (NIU) by-pass architecture places the NIU on its own circuit card and exclusive of by-pass switching (and relay) components, which are installed in the equipment shelf, proper, so that physical removal of the NIU card will leave the by-pass circuitry intact. The by-pass circuit responds to an abnormality of the NIU card, such as malfunction or physical removal of the NIU from its card slot, and also to a power supply failure. It also contains an indicator to draw attention to a failed NIU, increasing the likelihood that someone will notice a damaged card.

Abstract: The interface apparatus has a connector-receiving unit for receiving a connector that is electrically connected via a conductor to a first device. The connector has a receiving opening corresponding to the conductor. The apparatus further has a port for receiving a cable terminator electrically connected to a second device that is configured to communicate with the network component. Furthermore, the apparatus has a component electrically connected to the port that has a conductive probe movably positioned with respect to the receiving opening corresponding to the conductor of the connector. The component has an actuation component that moves the conductive probe into the receiving opening of the connector when actuated thereby establishing a conductive path between the first device and the second device.

Abstract: An integrated access device is automatically configured to conduct packetized voice and data communications between a customer's voice/data equipment and a digital communications switch. For this purpose, the IAD's communication control processor is programmed to perform an automated analysis of the digital communications link and thereby identify communication interface circuits such as DSLAM and voice gateway units, that have been installed by the service provider. It then automatically configures the communication parameters of the IAD for communication compatibility with the communication interface circuits.

Abstract: A regulated power supply interface has a current feedback and voltage level shift circuit that monitors power supply output (load) current and controllably diverts current to a current reference node. A differential amplifier-based, voltage feedback and voltage level shift circuit monitors the load voltage and controllably diverts output current to the current reference node. A current mode setpoint circuit has multiple voltage dropping current paths, through one or more of which a summation of the diverted load currents are programmably directed, to generate a control voltage for controlling the operation of a pulse width modulator unit of the regulated power supply.

Abstract: A comparator-based switchmode power converter monitors the most negative of the tip and ring line voltages, to control the supply voltage to a SLIC. The voltage applied to the SLIC's power terminals is slightly higher than the sensed voltage for different loop signaling conditions, including loop start, ground start balanced ringing. The switchmode converter includes a comparator coupled to a DC-DC output node downstream of a MOSFET switch installed in a DC supply rail of a source of DC supply voltage, and coupled to a power supply terminal of the SLIC. The comparator is also coupled to a set point node, which is coupled through a voltage offset path to each of tip and ring portions of the telephone line.

Abstract: Unaligned accesses to memory are circumvented by an address exception handler mechanism, which decodes an exception-triggering instruction, and reads from or writes to, in a byte-by-byte manner, addressed portions of memory which are unaligned with an addressing scheme through which accesses to memory may be performed, and thereby give rise to unaligned memory access exceptions. The handler simulates the execution of the instruction with reference to an exception stack frame, to which the contents of all registers at the time of the unaligned address exception are saved. This allows the handler to controllably define values that are restored into registers during the processor's execution of a general exception vector. After handling the exception, program execution transitions to the next instruction that directly follows the exception-causing instruction.

Abstract: A voice path direct memory access (DMA)-based packet generation mechanism writes digitally encoded voice samples directly into prescribed subportions of a preallocated portion of random access memory, to avoid interrupting a main processor for the purpose. A pointer to a respective buffer space subportion is presented to a protocol stack, so that one or more overhead bytes for the stored voice samples can be generated and written into adjacent address space of the preallocated portion of random access memory. The contents of the preallocated memory space are then serialized out for transmission to a destination receiver.

Abstract: A search path recovery mechanism for a sequential decoder employs a prescribed self-concatenated “Loeliger” convolutional code, that is either decodable by the sequential decoder for data recovery, or is decodable (although sub-optimally) by a Viterbi decoder as an adjunct to the sequential decoder to improve statistics during path recovery. The Viterbi decoder is incorporated in an alternate decoder which includes metric calculators, that compute branch metrics, that are alternately coupled to the Viterbi decoder, operating at twice the symbol rate. Using estimate bits from the Viterbi decoder, a syndrome former estimates the recovered state and generates an estimate of the validity of the recovered state. Their validity is verified by a path recovery detector, which operates as a zero error detection filter by summing a prescribed number of previous syndrome former outputs.

Abstract: Relatively low cost asymmetric digital subscriber line (ADSL) service and auxiliary POTS service are delivered over extended distances (e.g., at least 20–25 kft), by a hybrid ADSL-SDSL architecture insertable between central office and remote sites of an ADSL system. Central office and remote site transceivers employ trellis coded pulse amplitude modulation and a data rate that conforms with the signal transport capability of an extended distance symmetric DSL (SDSL) loop, while providing a 64K POTS channel. The central office and remote site transceivers controllably insert idle asynchronous transfer mode (ATM) cells in upstream and downstream ADSL channels to compensate for timing differences with ADSL equipment.

Abstract: A digital subscriber loop line card-installed mechanism conducts parametric measurements on the wireline to which the line card is connected, and adjusts taps of an echo cancellation operator in accordance with the response of the wireline to an electrical stimulus imparted to the wireline. The echo canceler tap coefficients are then processed to determine the location of a fault, such as a short circuit, open-circuit and the like, on the wireline. Fault information measurement data is then reported to a supervisory control location, which dispatches the appropriate technician to resolve the cause of the problem.

Abstract: Whether or not protection circuitry for a span-powered remote digital subscriber loop unit is properly connected to earth ground is determined by the deliberate assertion and detection of a ground fault from a central office line card location. The span-powered remote unit is augmented to place a controllable conduction path in circuit with the span-powered loop and an earth ground pin. If the earth ground pin has been properly connected to earth ground, applying the conductive path will place a ground fault on the span, which is detected by a ground fault detector within the central office line card. If the ground fault detector does not detect a ground fault in response to the application of the conductive path, the line card forwards a negative ground fault event message to a test center, so that a service technician may be dispatched to the remote unit to correct the problem.

Abstract: A redundant communication system contains a principal transceiver and a back-up transceiver to be controllably substituted for the principal transceiver. A monitor protection switch, which controls swapping the two transceivers, has an RF loopback test circuit that is switchably coupled to whichever transceiver is the back-up. The RF loopback test circuit monitors the operational capability of the back-up transceiver, and provides an indication of its functionality. If the back-up transceiver is defective, corrective action can be taken in advance of a potential operational failure of the principal transceiver. As long as the RF loopback test circuit indicates proper operational capability of the back-up transceiver, the redundant transceiver can be immediately switched in place of the principal transceiver.

Abstract: A binary decision tree-based arbitration scheme executable by a control processor of a time division multiplex (TDM)-based communication system is operative to select the next packet to be transmitted from a plurality of virtual circuits, any number of which may have one or more packets awaiting transmission over a serialized digital communication link. The transmission priority scheme contains N+1 sets of nodes containing 2N+1?1 nodes. A respective ith set of nodes comprises 2i?1 nodes, wherein i is greater than or equal to 1, and less than or equal to N+1. The nodes of a given set are connected to those of an adjacent set by binary-split branches. For each of the 2N leaf nodes of the decision tree, information is stored representative of the transmission priority of a packet awaiting transmission from its associated communication port.

Abstract: An echo canceler for a fractionally spaced telecommunication receiver employs a signal estimator, which generates a fractionally spaced representation of a received information signal that has been subjected to Tomlinson preceding. The output of the signal estimator is differentially combined with fractionally spaced outputs of the echo canceller, so as to effectively remove the contribution of the received information signal from the echo cancellation update operation. As a result, the echo update signal will consist primarily of the residual echo and the noise from the wireline/loop. The error signal can be used at the fractional spacing rate to update all of the echo canceler coefficients, largely without interference from the much larger received information signal. This allows a higher echo canceler gain than that currently incorporated into HDSL2 echo canceler updates.

Abstract: A method and apparatus for adaptively adjusting the parameters of a timing loop based upon frequency errors between a data signal and a receiver's clock that is being used to sample the data signal are provided by the present invention. In accordance with the invention, the timing loop parameters are first set to an initial set of parameter values. A current frequency error between the data signal and the receiver's clock is calculated. The approximate average value of the frequency error is then determined. After a predetermined amount of time, the absolute value of the difference between the average frequency error and the current frequency error is examined. If the absolute value of the difference is less than a specified threshold, the timing loop parameters are reset to a second set of parameter values contained in a memory. The timing loop parameters are then reset to a third set of parameter values after a second interval of time.

Abstract: Adaptive clock recovery for the receiving entity of a communication system transporting constant bit-rate (CBR) services over an asynchronous transfer mode (ATM) or ATM-like network is performed by a digital phase locked loop (DPLL). The recovered clock is based on the DPLL's phase detector's count of high frequency service clock cycles between transitions in an input signal representative of instances of receipt of ATM cells subject to cell delay variations through the network, and a reference clock signal whose frequency is a prescribed fraction of that of the output clock. The DPLL's VCO function is an increment/decrement of the service clock frequency, which avoids constraining the operation of a high performance modem (such as a V.90 modem).

Abstract: A multi-circuit emulating line card is installable in a single line card slot of the backplane of digital switch, and is configured to emulate the functionality of each of a plurality of digital switch line cards, respectively associated with plural digital subscriber circuits served by the switch. In the course of emulating these plural line cards, the multi-circuit line card provides connectivity between each digital subscriber circuit and a digital carrier communication link to plural digital subscriber loop circuits, such as BRITE cards of a remote terminal site. The line card of the invention also includes network and subscriber circuit-associated metallic link impedance simulation circuits for terminating a metallic test bus.

Abstract: A central office transceiver-installed current limiter and regulator provides fault isolation and transient load isolation in a wireline communication network, having multiple transceivers connected by respective span-powered wirelines to a common power source at the central office. Using a current-sense resistor and controlled switch in series with the wireline, the current-limiter and regulator processes input electrical power from the power source prior to coupling that power to a remote transceiver. To prevent overheating and substantial power dissipation in the current-limiting circuitry in the event of a prolonged fault condition, the controlled switch is alternately turned on and off.