Abstract: Various die stacks and methods of creating the same are disclosed. In one aspect, a method of manufacturing is provided that includes mounting a first semiconductor die on a second semiconductor die of a first semiconductor wafer. The second semiconductor die is singulated from the first semiconductor wafer to yield a first die stack. The second semiconductor die of the first die stack is mounted on a third semiconductor die of a second semiconductor wafer. The third semiconductor die is singulated from the second semiconductor wafer to yield a second die stack. The second die stack is mounted on a fourth semiconductor die of a third semiconductor wafer.

Abstract: A method and device for reducing power during an instruction lane divergence includes idling an inactive execution lane during the lane divergence.

Abstract: Different strain-inducing semiconductor alloys may be incorporated into the drain and source areas of different transistors in sophisticated semiconductor devices by at least patterning the corresponding cavities in a common manufacturing sequence. Thus, the etch process may be performed on the basis of a high degree of uniformity and the subsequent epitaxial growth processes may, in some illustrative embodiments, be accomplished on the basis of only one additional lithography step.

Abstract: Improved memory management in a processor is provided using garbage collection utilities. The processor includes higher performance memory units and lower performance memory units and a memory management unit. The memory management unit includes a garbage collection utility programmed to identify high use memory blocks and low use memory blocks within the higher and lower performance memory units. The memory management unit is also configured to move the high use memory blocks to higher performance memory and move the low use memory blocks to lower performance memory. The method comprises determining performance characteristics of available memory to identify higher performance memory and lower performance memory. Next memory block use metrics are analyzed to identify high use memory blocks and low use memory blocks. Finally, high use memory blocks are moved to the higher performance memory while the low use memory blocks are moved to the lower performance memory.

Abstract: Systems and methods for synchronizing thread wavefronts and associated events are disclosed. According to an embodiment, a method for synchronizing one or more thread wavefronts and associated events includes inserting a first event associated with a first data output from a first thread wavefront into an event synchronizer. The event synchronizer is configured to release the first event before releasing events inserted subsequent to the first event. The method further includes releasing the first event from the event synchronizer after the first data is stored in the memory. Corresponding system and computer readable medium embodiments are also disclosed.

Abstract: Embodiments directed to an autonomous graphics processing unit (GPU) scheduler for a graphics processing system are described. Embodiments include an execution structure for a host CPU and GPU in a computing system that allows the GPU to execute command threads in multiple contexts in a dynamic rather than fixed order based on decisions made by the GPU. This eliminates a significant amount of CPU processing overhead required to schedule GPU command execution order, and allows the GPU to execute commands in an order that is optimized for particular operating conditions. The context list includes parameters that specify task priority and resource requirements for each context. The GPU includes a scheduler component that determines the availability of system resources and directs execution of commands to the appropriate system resources, and in accordance with the priority defined by the context list.

Abstract: Embodiments of the invention as described herein provide a solution to the problems of conventional methods as stated above. In the following description, various examples are given for illustration, but none are intended to be limiting. Embodiments include a frame processor module in a graphics processing system that examines the intra-coded and inter-coded frames in an encoded video stream and initiates migration of decoding and rendering functions to a second graphics processor from a first graphics processor based on the location of intra-coded frames in a video stream and the composition of intermediate inter-coded frames.

Abstract: Embodiments of a software video encoder with GPU acceleration include a software encoder that partitions video processing tasks and assigns them to both a graphics processing unit (GPU) and a central processing unit (CPU). The partitioning and assigning is configurable for operation in different modes. The modes include a mode in which the total time for video processing (such as when transcoding a large existing file) is reduced, a mode in which less CPU cycles are consumed, thus freeing the CPU for other work, ad mode in which the latency of processing (e.g., for video conferencing) is reduced, and a mode in which information from a game or other real-time activity being displayed on the screen is encoded.

Abstract: Embodiments of the video data capture and stream method comprise intercepting a flip function call comprising a call by the video application to flip frames between a display and a buffer, grabbing a copy of the current frame that would normally be processed by a central processing unit (CPU), placing the copy in a queue for processing by a graphics processing unit (GPU), wherein processing by the GPU is significantly faster than processing by the CPU.

Abstract: The present invention provides a system and methodology for dummy-dispensing resist though a dispense head while mitigating waste associated with the dummy-dispense process. The dummy dispensed resist is returned to a reservoir from which it was taken. Between substrate applications, the dispense head can be positioned to dispense resist into a return line. The flow of resist from the dispense head keeps resist from drying at the dispense head. By funneling the dummy-dispensed resist into a return line with low volume, for example, waste from the dummy-dispensing process can be mitigated.

Abstract: According to an example embodiment of the present invention a semiconductor die having a resistive electrical connection is analyzed. Heat is directed to the die as the die is undergoing a state-changing operation to cause a failure due to suspect circuitry. The die is monitored, and a circuit path that electrically changes in response to the heat is detected and used to detect that a particular portion therein of the circuit is resistive. In this manner, the detection and localization of a semiconductor die defect that includes a resistive portion of a circuit path is enhanced.

Abstract: Management of multiple types of empty carriers in automated material handling systems. In one embodiment, an automated material handling system (AMHS) includes a plurality of material carriers including a plurality of empty carriers classified into two or more types and one or more stock areas, each including a plurality of bins for storing material carriers. Each stock area is associated with one or more thresholds for each empty carrier type. The AMHS further includes a control system coupled to a first one of the stock areas for computing an empty percentage for each empty carrier type. The empty percentage for a particular empty carrier type is the percentage of bins of the first one stock area which contain empty carriers of the particular type.

Abstract: According to an example embodiment, the present invention is directed to a new and efficient method for bringing at least two items together from independent locations via separate paths in a computer controlled manufacturing environment. Using the computer, the probabilities for pickup and delivery of each of the two items are generated and used to determine an efficient manner in which to bring the items together via the separate paths.

Abstract: A reticle sorter and a semiconductor fabrication facility employing one or more reticle sorters is provided. The reticle sorter(s) generally lies between a reticle storage system and a group of one or more photolithography exposure tools (e.g., steppers) and is configured for sorting reticles in one or more cassettes. The use of the reticle sorter provides sorting functionality apart from the reticle storage system and typically closer to the group of photolithography steppers with which it is associated. This can, for example, significantly increase the throughput of semiconductor wafers through the associated photolithography exposure tools as well as in the semiconductor fabrication plant as a whole.

Abstract: According to an example embodiment, a system for testing a semiconductor die is provided. The semiconductor die has circuitry on one side and silicon on an opposite side, and the opposite side may be AR coated. The opposite side is thinned, the die is powered, and a portion of the circuitry is heated to cause a reaction (e.g., a circuit failure or recovery) in a target region. The circuitry is monitored, and the circuit that reacts to the heat is detected and analyzed.

Abstract: A semiconductor device is analyzed and manufactured using a heat-exchange probe. According to an example embodiment of the present invention, a heat-exchange probe is controlled to exchange heat to a portion of a semiconductor device using sub-micron resolution. In one implementation, sub-micron resolution is achieved using a navigational arrangement, such as microscope, adapted to direct light to within about one micron of a target circuit portion on a plane of the device. In another implementation, a physical heat probe tip (e.g., a metal probe having about a one micron diameter probe tip) is navigated to a selected portion of the device using sub-micron navigational resolution. In each of these implementations, as well as others, the heat exchange is preponderantly confined to within about a one micron radius of a target portion of circuitry on lateral plane of the device.

Abstract: According to one aspect of the disclosure, the present invention provides methods and arrangements for controlling supply process gas to a process chamber for use in the manufacturing industry. Methods include controlling the operation of a valve coupled to the supply process gas line in a way such that pressure bursts in the process chamber due to the operation of the valve are reduced, or even eliminated.

Abstract: An asymmetric double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a first fin formed on a substrate; a second fin formed on the substrate; a first gate formed adjacent first sides of the first and second fins, the first gate being doped with a first type of impurity; and a second gate formed between second sides of the first and second fins, the second gate being doped with a second type of impurity. An asymmetric all-around gate MOSFET includes multiple fins; a first gate structure doped with a first type of impurity and formed adjacent a first side of one of the fins; a second gate structure doped with the first type of impurity and formed adjacent a first side of another one of the fins; a third gate structure doped with a second type of impurity and formed between two of the fins; and a fourth gate structure formed at least partially beneath one or more of the fins.

Abstract: A method of detecting a charge stored on a charge storage region of a first dual bit dielectric memory cell within an array of dual bit dielectric memory cells comprises applying a source voltage to a first bit line that is the source of the selected memory cell and applying a drain voltage to a second bit line that forms a drain junction with the channel region. The source voltage may be a small positive voltage and the drain voltage may be greater than the source voltage. A read voltage is applied to a selected one of the word lines that forms a gate over the charge storage region and a bias voltage is applied to non-selected word lines in the array. The bias voltage may be a negative voltage.

Abstract: A method for scheduling activities in a manufacturing system includes defining a plurality of observed states associated with the manufacturing system. State estimates are generated for the observed states. Uncertainty values for the state estimates are generated. A plurality of candidate schedules for performing activities in the manufacturing system is identified. Changes to the uncertainty values are predicted based on the candidate schedules. One of the candidate schedules is selected based on the predicted changes to the uncertainty values.