Abstract: A semiconductor packaging apparatus for preventing cracking and delamination in a packaged semiconductor chip by controlling the die attach fillet height. Specifically, the present invention controls the die attach material height, thereby controlling the die attach fillet height, and thereby reducing shear stress in the die itself. Advantages of the present invention include increasing wire-bond reliability and package reliability without the need for requalification of existing products. By using currently qualified molding compounds and die attach epoxies in conjunction with the present technique for controlling the die attach epoxy height in order to control the die attach fillet height, the overall assembly process may be maintained. Thus, neither thermal performance nor electrical performance is compromised.

Abstract: Several different embodiments of a semiconductor device and a heat sink assembly and are described, as well as methods for forming the embodiments. Methods for coupling corresponding embodiments of the heat sink assembly and the semiconductor device to form an electronic apparatus are also described, wherein the electronic apparatus includes a compliant support for supporting a heat sink. The semiconductor device includes an integrated circuit (IC) mounted upon an upper surface of a substrate. In a first embodiment of the semiconductor device, the compliant support is positioned about an outer region of the upper surface of the substrate surrounding the IC. In a second embodiment of the heat sink assembly, the compliant support is attached to an outer region of an underside surface of the heat sink. The compliant support responds to a compressive first force by producing a spring-like second force which opposes the first force.

Abstract: Improved etch selectivity, barrier metal wetting and reduced interconnect capacitance are achieved by implementing damascene processing employing a graded middle etch stop layer comprising a first silicon carbide layer, a silicon-rich layer on the first silicon carbide, and a second silicon carbide layer on the silicon-rich layer. Embodiments include sequentially depositing a porous low-k dielectric layer over a lower capped Cu line, depositing the graded middle-etch stop layer, depositing a porous low-k dielectric layer on the graded middle-etch stop layer, forming a dual damascene opening exposing the silicon-rich surface at the bottom of the trench opening, depositing a seed layer, depositing a barrier middle layer, such as Ta or a Ta/TaN composite, and filling the opening with Cu.

Abstract: A process for fabricating a semiconductor device, the process includes providing a semiconductor substrate having an oxide-nitride-oxide layer thereon and a patterned resist layer overlying the oxide-nitride-oxide layer, wherein the oxide-nitride-oxide layer includes a first oxide layer, a nitride layer overlying the first oxide layer, and a second oxide layer overlying the nitride layer. The process further includes, performing an isotropic etch on the oxide-nitride-oxide layer to remove a portion of the oxide-nitride-oxide layer.

Abstract: A method and system for providing a plurality of lines in a semiconductor memory device is disclosed. The method and system include providing a semiconductor substrate, providing a plurality of lines and providing an adjacent feature. The plurality of lines includes an adjacent line adjacent to the adjacent feature. The each of the plurality of lines has a line width that is substantially the same for each of the plurality of lines. The plurality of lines is preferably formed utilizing a mask to print a physical mask for the plurality of lines and the adjacent feature. The mask includes a mask assist feature between at least a first polygon for the adjacent line and at least a second polygon for the adjacent feature. The mask assist feature has a size that is sufficiently large to affect the width of the adjacent line and that is sufficiently small to prevent a corresponding feature from being printed on the physical mask.

Abstract: Damaged low-density silicon oxide-based films having an Si—O backbone are repaired using a method for driving a self-limiting healing process. According to an example embodiment of the present invention, a deposition precursor and an oxidizer are introduced to a damaged side wall region of a low-density silicon oxide-based film. The unstable damaged portion of the film reacts with the deposition precursor and a thin repair film is grown within the interfacial layer of the damaged film. The repair film provides a strengthened interface, protects the underlying sensitive material from further chemical damage, and can improve the ability to integrate the film.

Abstract: According to one aspect of the disclosure, the present invention provides methods and arrangements for milling the substrate of a semiconductor device and exposing a selected region in the substrate. A laser is directed at a selected area of the back side of the device to create a small marker to be used for alignment during the milling process. The substrate is then milled to expose the selected area within the substrate, using the marker as alignment.

Abstract: A submicron semiconductor device having a self-aligned channel stop implant region, and a method for fabricating the semiconductor device using a trim and etch is disclosed. The semiconductor device includes a plurality of active regions separated by insulating regions. The method for fabricating the device includes depositing a nitride over a substrate and selectively covering the active regions with a mask, wherein the mask extends beyond boundaries of the active regions to narrow the width of the insulating regions. Thereafter, a channel stop implant is performed to form channel stops. The mask is then trimmed to the boundaries of the active regions after formation of the channel stops, followed by etching the nitride in exposed areas of the mask. Field oxide is then grown in the insulating regions, whereby the field oxide is self-aligned to the channel stops.

Abstract: A method and device for avoiding unnecessary data broadcasts by detecting the presence of additional cache-equipped bus-masters is provided. The device includes a master bus-master equipped with a local cache arrangement for caching data originating in a system memory. The master bus-master communicates with the system memory over a bus, and is coupled to a control line at an input. Any cache-equipped slave bus masters that are caching data with the system memory are coupled to the control line by an output and are configured to generate a signal at the output to drive the control line to a predetermined state to indicate that they are caching data. The master bus-master detects the state of the control line and determines whether the data being buffered in its local cache arrangement is shared based upon the state of the control line.

Abstract: A self-latching logic gate is disclosed which includes a first logic gate circuit for generating an output signal representative of a function of two or more input signals. The first logic gate circuit includes a first logic gate having at least two transistors, each transistor having first, second and third terminals. The first terminals of each transistor are connected to provide an output terminal for the self-latching logic gate and the first logic gate circuit. The second terminals of the transistors provide first and second data input terminals for the logic gate circuit. The third terminals of each transistor are connected to a common termination (i.e. ground). First and second complementary mode transistors are provided.

Abstract: A four device cell is disclosed for an electrically erasable programmable logic device. The four devices include a floating gate tunnel capacitor, a floating gate read transistor having its floating gate and control gate connected respectively to the floating gate and control gate of the tunnel capacitor, a read select transistor for selectively coupling the drain of the floating gate read transistor to a product term output in response to an input term, and a write select transistor for selectively coupling the drain of the floating gate tunnel capacitor to a write data line in response to the signal on a write select line. During sensing, the control gates of all the floating gate tunnel capacitors are kept at a constant voltage V.sub.cg. The drains of all of the floating gate tunnel capacitors are also kept at a constant voltage V.sub.WDL chosen to minimize read disturb on the tunnel capacitor. Preferably V.sub.WDL =V.sub.cg .multidot.V.sub.

Abstract: A digital filter receive circuit for use with a StarLAN coded data transceiver includes three D-type flip-flops and four NAND logic gates. The digital receive line filter circuit is capable of being implemented as part of a single monolithic integrated circuit containing the transceiver, thereby producing a miniaturized and compact structure.