Abstract: A filling paste structure and process of wafer level package is disclosed. The process comprises filling an adhesive material to fill among plurality of dice and cover the plurality of dice. The pluralities of dice are adhered to glue pattern with viscosity in common state formed on a removable substrate. A rigid substrate is coated by adhesive material to adhere the dice. Then, pluralities of dice are departed from the glue pattern by a special environment after attaching the rigid base substrate.

Abstract: A wafer level package comprises a wafer having a plurality of dice formed thereon; a thinner metal cover with a cavity formed therein attached on the wafer by an adhesive material to improve thermal conductivity of the package. A protection film is formed on back side of the metal cover and filled into the cavity, thereby facilitating for laser marking and obtaining a better sawing quality of the package.

Abstract: A trace structure with a particular profile to eliminate stress concentration and the fabricating method thereof are provided. The trace structure includes a conductive line, a seed layer, and a protection layer, wherein an upper part of the trace line is covered by the protection layer to prevent sharp edges caused by over etching in the fabrication of the conductive line. Hence, the stress concentration due to the sharp edges in the trace structure is diminished and the reliability of packaging structures or other devices applying the trace structure is assured.

Abstract: The present invention discloses a structure of package including: a substrate with a die receiving through hole, a connecting through hole structure and a first contact pad; a die having micro lens area disposed within the die receiving through hole; a transparent cover covers the micro lens area; a surrounding material formed under the die and filled in the gap between the die and sidewall of the die receiving though hole; a dielectric layer formed on the die and the substrate; a re-distribution layer (RDL) formed on the dielectric layer and coupled to the first contact pad; a protection layer formed over the RDL; and a second contact pad formed at the lower surface of the substrate and under the connecting through hole structure.

Abstract: The present invention provides a structure of elastic dielectric layers with certain through holes adjacent to the angle of a RDL of WLP to absorb the stress. The elastic dielectric layer is made from silicone based materials with specific range of CTE, elongation rate and hardness, which can improve the mechanical reliability of the structure during temperature cycling test. The CTE difference between the RDL and the elastic dielectric material still may cause the elastic dielectric layer crack; to solve this problem, The present invention further provides a structure of dielectric layers with certain open through holes adjacent to the curve portion of a RDL of WLP which can reduce the stress accumulated at area of the dielectric layer adjacent to the RDL/dielectric layer interface to solve the crack problem of the dielectric layer.

Abstract: The present invention provides a semiconductor device package with the multi-chips comprising a substrate with at least a die receiving through hole, connecting through holes structure and first contact pads on an upper surface and second contact pads on a lower surface of the substrate. At least a first die having first bonding pads is disposed within the die receiving through hole. A first adhesion material is formed under the die and a second adhesion material is filled in the gap between the die and sidewall of the die receiving though hole of the substrate. Then, a first bonding wire is formed to couple the first bonding pads and the first contact pads. Further, at least a second die having second bonding pads is placed on the first die. A second bonding wire is formed to couple to the second bonding pads and the first contact pads. A dielectric layer is formed on the first and second bonding wire, the first and second die and the substrate.

Abstract: The present invention provides a structure of package comprising a substrate with a die receiving cavity formed within an upper layer of the substrate, wherein terminal pads are formed on the upper surface of the substrate, the same plain as the micro lens. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. A re-distribution metal layer (RDL) is formed on the dielectric layer and coupled to the die. An opening is formed within the dielectric layer and a top protection layer to expose the micro lens area of the die for Image Sensor chip. A protection layer (film) be coated on the micro lens area with water repellent and oil repellent to away the particle contamination. A transparent cover with coated IR filter is optionally formed over the micron lens area for protection.

Abstract: The present invention provides an efficient test method and system for testing the IC package, such as BGA types of packages. With the present invention, manufacturer can have an easier way in testing various types of packages, including newer types. Manufacturer also can get the testing outcome which is more accurate. Furthermore, the present invention helps the manufacturer to achieve a significant improvement in IC packaging process.

Abstract: The present invention provides a package structure and a method for forming the same. The structure comprises a substrate with contact pads and through holes filled with conducting metals for performing heat dissipation and ground shielding A chip with bonding pads is attached on the contact pad by an adhesive with high thermal conductivity to achieve heat dissipation. A RDL is formed on the substrate and the chip to couple the bonding pad and the contact pad formed on the substrate. The structure of present invention can improve the thickness thereof, and the heat dissipation and ground shielding of the structure are enhanced. Furthermore, the structure can achieve package on package (PoP) structure.

Abstract: The present invention provides a semiconductor device package with the die receiving through hole and connecting through hole structure comprising a substrate with a die receiving through hole, a connecting through hole structure and a first contact pad. A die is disposed within the die receiving through hole. An adhesion material is formed under the die and filled in the gap between the die and sidewall of the die receiving though hole. Further, a wire bonding is formed to couple to the bonding pads and the first contact pad. A dielectric layer is formed on the wire bonding, the die and the substrate. A second contact pad is formed at the lower surface of the substrate and under the connecting through hole structure.

Abstract: A chip packaging structure comprising a chip, a plurality of conductive pillars surrounding the chip, an encapsulation encapsulating the chip and the conductive pillars, and a connecting layer is provided. The encapsulation has a first side and a second side corresponding to the first side. The connecting layer is disposed at the first side of the encapsulation and electrically connected between the chip and the conductive pillars. Furthermore, a chip packaging process accompanying the chip packaging structure is also provided. The chip packaging structure is more useful and powerful and is suitable for various chip packaging applications, and the chip packaging process can reduce the manufacturing time and save the production cost.

Abstract: The present invention discloses a structure of package comprising a substrate with at least one die receiving through holes, a conductive connecting through holes structure and a contact pads on both side of substrate. At least one die is disposed within the die receiving through holes. A first material is formed under the die and second material is formed filled in the gap between the die and sidewall of the die receiving though holes. Dielectric layers are formed on the surface of both side of the die and the substrate. Redistribution layers (RDL) are formed on the both sides and coupled to the contact pads. A protection bases are formed over the RDLs.

Abstract: An image sensor multi-chips package structure, includes a first package including a first chip with image sensors having first bonding pads and micro lens on a first active surface, a first die receiving window and first conductive inter-connecting through holes penetrated from a first upper contact pads on a first upper surface of the first chip to a first lower contact pads on a first lower surface of the first chip, wherein a first upper build up layer on the active surface of the first chip coupling from the first bonding pads to the first upper contact pads; a second package comprising a second chip having second bonding pads on a second active surface, a second die receiving window and second conductive inter-connecting through holes penetrated from a second upper contact pads of a second upper surface of the second chip to a second lower contact pads on a second lower surface of the second chip, wherein a second upper build up layers on the second upper surface for coupling from the second bonding pads

Abstract: The present invention provides a semiconductor device protective structure. The structure comprises a die with contact metal balls formed thereon electrically coupling with a print circuit board. A back surface of the die is directly adhered on a substrate and a first buffer layer is formed on the substrate. The substrate is configured over a second buffer layer such that the second buffer layer substantially encompasses the whole substrate to decrease damage to the substrate when the side of the substrate is collided with an external object.

Abstract: The present invention provides a semiconductor device package with the multi-chips comprising a substrate with a die receiving through hole, a conductive connecting through holes structure and coupled the first contact pads on an upper surface and second contact pads on a lower surface of the substrate through a conductive connecting through holes. A first die having first bonding pads is disposed within the die receiving through hole. A first adhesion material is formed under the die and a second adhesion material is filled in the gap between the die and sidewall of the die receiving though holes of the substrate. Then, a first conductive wire is formed to couple the first bonding pads and the first contact pads. Further, a second die having second bonding pads is attached on the first die. A second conductive wire is formed to couple the second bonding pads and the first contact pads. A plurality of dielectric layer is formed on the first and second bonding wire, the first and second die and the substrate.

Abstract: The present invention provides a semiconductor device package with the multi-chips comprising a substrate with at least a die receiving through hole, connecting through holes structure and first contact pads on an upper surface and second contact pads on a lower surface of the substrate. At least a first die having first bonding pads is disposed within the die receiving through hole. A first adhesion material is formed under the die and a second adhesion material is filled in the gap between the die and sidewall of the die receiving though hole of the substrate. Then, a first bonding wire is formed to couple the first bonding pads and the first contact pads. Further, at least a second die having second bonding pads is placed on the first die. A second bonding wire is formed to couple to the second bonding pads and the first contact pads. A dielectric layer is formed on the first and second bonding wire, the first and second die and the substrate.

Abstract: The present invention provides a structure of multi-chips package and Method of the same comprising a substrate with a pre-formed die receiving cavity formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and an elastic dielectric layer filled into a gap between the die and the substrate to absorb thermal mechanical stress; therefore the thickness of the package is reduced and the CTE mismatch of the structure is reduced. The present invention also provides a structure for SIP with higher reliability and lower manufacturing cost. the process is simpler and it is easy to form the multi-chips package than the traditional one. Therefore, the present invention discloses a fan-out WLP with reduced thickness and good CTE matching performance.

Abstract: The present invention provides a structure of package comprising a substrate with a die receiving cavity formed within an upper layer of the substrate, wherein terminal pads are formed on the upper surface of the substrate, the same plain as the micro lens. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. A re-distribution metal layer (RDL) is formed on the dielectric layer and coupled to the die. An opening is formed within the dielectric layer and a top protection layer to expose the micro lens area of the die for Image Sensor chip. A protection layer (film) be coated on the micro lens area with water repellent and oil repellent to away the particle contamination. A transparent cover with coated IR filter is optionally formed over the micron lens area for protection.

Abstract: The present invention provides a structure of package comprising a substrate with a die through hole and a contact through holes structure formed there through, wherein a terminal pad is formed under the contact through hole structure and a contact pad is formed on a upper surface of the substrate. A die having a micro lens area is disposed within the die through hole by adhesion. A wire bonding is formed on the die and the substrate, wherein the wire bonding is coupled to the die and the contact pad. A protective layer is formed to cover the wire bonding. A transparent cover is disposed on the die within the die through hole by adhesion to expose the micro lens area. Conductive bumps are coupled to the terminal pads.

Abstract: The present invention provides an image sensor module structure comprising a substrate with a die receiving cavity formed within an upper surface of the substrate and conductive traces within the substrate and a die having a micro lens disposed within the die receiving cavity. A dielectric layer is formed on the die and the substrate, a re-distribution conductive layer (RDL) is formed on the dielectric layer, wherein the RDL is coupled to the die and the conductive traces and the dielectric layer has an opening to expose the micro lens. A lens holder is attached on the substrate and the lens holder has a lens attached an upper portion of the lens holder. A filter is attached between the lens and the micro lens. The structure further comprises a passive device on the upper surface of the substrate within the lens holder.