Patents Assigned to Advanced Chip Engineering Technologies Inc.
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Publication number: 20080157398Abstract: The present invention provides a semiconductor device package having pseudo chips structure comprising a first substrate with die receiving through holes formed thereon; a first die having first bonding pads and a second die having second bonding pads disposed within the die receiving through holes, respectively; an adhesion material formed in the gap between the first and second die and sidewalls of the die receiving though holes of the first substrate; redistribution lines formed to couple the first contact pads formed on the first substrate to the first bonding pads and the second bonding pads, respectively; and a protection layer formed on the redistribution lines, the first die, the second die and the first substrate.Type: ApplicationFiled: June 26, 2007Publication date: July 3, 2008Applicant: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Jui-Hsien Chang, Chi-Chen Lee, Wen-Ping Yang
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Publication number: 20080073774Abstract: A chip package including a multilayer substrate, an adhesive core layer and a chip is provided. The multilayer substrate has a plurality of material layers. The adhesive core layer is disposed on the multilayer substrate. The chip is disposed in the adhesive core layer. The chip has an active surface exposed outside the adhesive core layer. The chip includes a plurality of bonding pads disposed on the active surface and a plurality of metal conductive bodies electrically connected to the bonding pads respectively.Type: ApplicationFiled: December 4, 2006Publication date: March 27, 2008Applicant: ADVANCED CHIP ENGINEERING TECHNOLOGY INC.Inventors: Wen-Kun Yang, Dyi-Chung Hu, Chih-Ming Chen, Hsien-Wen Hsu
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Patent number: 7342296Abstract: The present invention provides a separating process of a semiconductor device package of wafer level package. The method comprises a step of etching a substrate to form recesses. Then a buffer layer is formed on the first surface of the substrate, wherein the buffer layer is filled with the corresponding recesses to form infillings on adjacent the semiconductor device package. Dicing the wafer into individual package along substantial center of said infillings, the step may avoid the roughness on the edge of each die and also decrease the cost of the separating process.Type: GrantFiled: December 5, 2005Date of Patent: March 11, 2008Assignee: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Jui-Hsien Chang
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Patent number: 7339279Abstract: The method includes a step of picking and placing standard good dice on a base for obtaining an appropriate and wider distance between dice than the original distance of dice on a wafer. The method of the chip-size package comprises the steps of separating dice on a wafer and picking and placing the dice on a base and filling a first material layer on the base into a space among the dice on the base. A dielectric layer with first openings is patterned to expose a portion of a conductive line of the dice. A conductive material is filled into the first openings and on the dielectric layer. Subsequently, a second material layer is formed to have a second openings exposing the conductive material and then welding solder balls on the second openings.Type: GrantFiled: May 11, 2007Date of Patent: March 4, 2008Assignee: Advanced Chip Engineering Technology Inc.Inventor: Wen Kun Yang
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Patent number: 7335870Abstract: The method of forming image sensor protection comprises attaching a glass on a tape and scribing the glass with lines to define cover zones on the glass, the glass is then break by a rubber puncher followed by forming glue on the edge of the cover zones. The glass is bonded on a wafer with an image sensor to align the cover zones to a micron lens area of the image sensor, and then the tape is removed from the wafer, thereby forming glass with cover zones on the image sensor.Type: GrantFiled: October 6, 2006Date of Patent: February 26, 2008Assignee: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Jui-Hsien Chang, Hsien-Wen Hsu
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Publication number: 20080020511Abstract: The present invention discloses an image sensor module and forming method of wafer level package. The image sensor module comprises a metal alloy base, a wafer level package, a lens holder, and flexible printed circuits (F.P.C.). The wafer level package having a plurality of image sensor dice and a plurality of solder balls is attached to the metal alloy base. A plurality of lens are placed in the lens holder, and the lens holder is located on the image sensor dice. The lens holder is placed in the flexible printed circuits (F.P.C.), and the flexible printed circuits (F.P.C.) has a plurality of solder joints coupled to the solder balls for conveniently transmitting signal of the image sensor dice. Moreover, the image sensor dice may be packaged with passive components or other dice with a side by side structure or a stacking structure.Type: ApplicationFiled: April 27, 2007Publication date: January 24, 2008Applicant: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Wen Pin Yang
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Publication number: 20080017941Abstract: The present invention discloses an image sensor module and forming method of wafer level package. The image sensor module comprises a metal alloy base, a wafer level package, a lens holder, and flexible printed circuits (F.P.C.). The wafer level package having a plurality of image sensor dice and a plurality of solder balls is attached to the metal alloy base. A plurality of lens are placed in the lens holder, and the lens holder is located on the image sensor dice. The lens holder is placed in the flexible printed circuits (F.P.C.), and the flexible printed circuits (F.P.C.) has a plurality of solder joints coupled to the solder balls for conveniently transmitting signal of the image sensor dice. Moreover, the image sensor dice may be packaged with passive components or other dice with a side by side structure or a stacking structure.Type: ApplicationFiled: July 19, 2006Publication date: January 24, 2008Applicant: Advanced Chip Engineering Technology Inc.Inventors: Wen Kun Yang, Wen Pin Yang
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Patent number: 7319043Abstract: The present invention provides an efficient test method and system for testing the IC package, such as BGA types of packages. With the present invention, manufacturer can have an easier way in testing various types of packages, including newer types. Manufacturer also can get the testing outcome which is more accurate. Furthermore, the present invention helps the manufacturer achieve a significant improvement in an IC packaging process.Type: GrantFiled: September 26, 2005Date of Patent: January 15, 2008Assignee: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Cheng Chieh Tai
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Publication number: 20070296065Abstract: The present invention provides a 3D electronic packaging unit having a conductive supporting substrate that can achieve multi-chip stacking through the signal contacts on the both sides of the unit. The packaging unit can be batched manufactured on wafers or substrates, and thus reduce the manufacturing cost of each individual packaging unit; moreover, the conductive supporting substrate can be utilized to provide signal transmission of the electronic elements, and the supporting substrate can be used as a ground terminal for the carried electronic elements to enhance electric performance of the electronic elements. The supporting substrate is also a good thermal conductor that can release effectively heat energy generated by the electronic elements and accumulated inside the package to the outside of the package along the substrate to enhance reliability of the packaging structure.Type: ApplicationFiled: June 27, 2006Publication date: December 27, 2007Applicant: Advanced Chip Engineering Technology Inc.Inventors: Ming-Chih Yew, Chang-Ann Yuan, Chan-Yen Chou, Kou-Ning Chiang
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Patent number: 7279782Abstract: A structure of package comprises a die placed on printed circuit board. A glass substrate is adhered on an adhesive film pattern to form an air gap area between the glass substrate and the chip. Micro lens are disposed on the chip. A lens holder is fixed on printed circuit board. The glass substrate can prevent the micro lens from particle contamination.Type: GrantFiled: January 5, 2005Date of Patent: October 9, 2007Assignee: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Chin-Chen Yang, Wen-Bin Sun, Jui-Hsien Chang, Chun Hui Yu, His-Ying Yuan
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Patent number: 7259468Abstract: The present invention discloses a structure of wafer level packaging. The structure comprises a first patterned isolation layer, a conductive layer and a second patterned isolation layer. The first patterned isolation layer is formed with a passivation layer of an IC (Integrated Circuit). The conductive layer is configured to have a curved or winding conductive pattern. The second patterned isolation layer is formed over the conductive layer to have a plurality of openings, and contact metal balls can be formed on the openings to electrically couple to a print circuit board.Type: GrantFiled: April 30, 2004Date of Patent: August 21, 2007Assignee: Advanced Chip Engineering Technology Inc.Inventor: Wen-Kun Yang
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Patent number: 7238602Abstract: The method includes a step of picking and placing standard good dice on a base for obtaining an appropriate and wider distance between dice than the original distance of dice on a wafer. The method of the chip-size package comprises the steps of separating dice on a wafer and picking and placing the dice on a base and filling a first material layer on the base into a space among the dice on the base. A dielectric layer with first openings is patterned to expose a portion of a conductive line of the dice. A conductive material is filled into the first openings and on the dielectric layer. Subsequently, a second material layer is formed to have a second openings exposing the conductive material and then welding solder balls on the second openings.Type: GrantFiled: October 26, 2004Date of Patent: July 3, 2007Assignee: Advanced Chip Engineering Technology Inc.Inventor: Wen Kun Yang
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Patent number: 7224061Abstract: A package structure including a device, an interconnecting element, a pad and a protecting element is provided. The device connects with a first end of the interconnecting element through the pad. The protecting element covers the pad and the first end of the interconnecting element.Type: GrantFiled: August 16, 2004Date of Patent: May 29, 2007Assignee: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Shih-Li Chen, Wen-Bin Sun, Ming-Hui Lin, Chao-Nan Chou, Chih-Wei Lin
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Publication number: 20070059866Abstract: To pick and place standard dies on a new base for obtaining an appropriate and wider distance between dies than the original distance of dies on a wafer. The package structure has a larger size of balls array than the size of the die by fan out type package. Moreover, the die may be packaged with passive components or other dies with a side by side structure or a stacking structure.Type: ApplicationFiled: November 13, 2006Publication date: March 15, 2007Applicant: ADVANCED CHIP ENGINEERING TECHNOLOGY INC.Inventors: Wen-Kun Yang, Wen-Pin Yang, Shih-Li Chen
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Patent number: 7176567Abstract: The present invention provides a semiconductor device protective structure. The structure comprises a die with contact metal balls formed thereon electrically coupling with a print circuit board. A back surface of the die is directly adhered on a substrate and a first buffer layer is formed on the substrate. The substrate is configured over a second buffer layer such that the second buffer layer substantially encompasses the whole substrate to decrease damage to the substrate when the side of the substrate is collided with an external object.Type: GrantFiled: July 6, 2005Date of Patent: February 13, 2007Assignee: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Kuang-Chi Chao, Cheng-hsien Chiu, Chihwei Lin, Jui-Hsien Chang
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Patent number: 7061106Abstract: The present invention discloses an image sensor module and forming method of wafer level package. The image sensor module comprises an isolating base, a wafer level package, a lens holder, and a F.P.C.. The wafer level package having a plurality of image sensor dies and a plurality of solder balls is attached to the isolating base. A plurality of lens are placed in the lens holder, and the lens holder is located on the image sensor dies. The lens holder is placed in the F.P.C., and the F.P.C. has a plurality of solder joints coupled to the solder balls for conveniently transmitting signal of the image sensor dies. Moreover, the image sensor dies may be packaged with passive components or other dies with a side by side structure or a stacking structure.Type: GrantFiled: April 28, 2004Date of Patent: June 13, 2006Assignee: Advanced Chip Engineering Technology Inc.Inventors: Wen-Kun Yang, Wen-Pin Yang
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Publication number: 20050247398Abstract: A tool of wafer level package comprises a first base, an elastic material and a second base. The elastic material is coated on the first base, and the elastic material has viscosity in common state to adhere a plurality of dies. The second base is coated by adhesive material to adhere the dies. The plurality of dies are departed from the elastic material by a special environment after adhering.Type: ApplicationFiled: June 20, 2005Publication date: November 10, 2005Applicant: Advanced Chip Engineering Technology Inc.Inventors: Wen Yang, Wen Yang, Shih-li Chen