Patents Assigned to Advanced Micro Device, Inc.
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Patent number: 12113946Abstract: A computer vision processing device is provided which comprises memory configured to store data and a processor. The processor is configured to store captured image data in a first buffer and acquire access to the captured image data in the first buffer when the captured image data is available for processing. The processor is also configured to execute a first group of operations in a processing pipeline, each of which processes the captured image data accessed from the first buffer and return the first buffer for storing next captured image data when a last operation of the first group of operations executes.Type: GrantFiled: August 29, 2022Date of Patent: October 8, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Radhakrishna Giduthuri, Michael L. Schmit
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Patent number: 12112270Abstract: A generator for generating artificial data, and training for the same. Data corresponding to a first label is altered within a reference labeled data set. A discriminator is trained based on the reference labeled data set to create a selectively poisoned discriminator. A generator is trained based on the selectively poisoned discriminator to create a selectively poisoned generator. The selectively poisoned generator is tested for the first label and tested for the second label to determine whether the generator is sufficiently poisoned for the first label and sufficiently accurate for the second label. If it is not, the generator is retrained based on the data set including the further altered data. The generator includes a first ANN to input first information and output a set of artificial data that is classifiable using a first label and not classifiable using a second label of the set of labeled data.Type: GrantFiled: August 9, 2021Date of Patent: October 8, 2024Assignee: Advanced Micro Devices, Inc.Inventor: Nicholas Malaya
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Patent number: 12113712Abstract: Dynamic network-on-chip traffic throttling, including: determining, by a detector module of a network-on-chip, that a predefined condition is met; sending, by the detector module, a signal to a mediator module of the network-on-chip; and sending, in response to the signal, by the mediator module, an indication to a plurality of agents to implement a traffic throttling policy.Type: GrantFiled: September 25, 2020Date of Patent: October 8, 2024Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Narendra Kamat, Vydhyanathan Kalyanasundharam, Gregg Donley, Ashwin Chincholi
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Patent number: 12111716Abstract: A processing device and method for efficient transitioning to and from a reduced power state is provided. The processing device comprises a plurality of components having assigned registers used to store data to execute a program and a power management controller, in communication with the plurality of components. The power management controller receives an indication that the plurality of components are idle, executes a process to enter a component into a reduced power state in response to receiving an acknowledgement from the component of a request from the power management controller to remove power to the component, and executes a process to exit the component from the reduced power state in response to the component being active.Type: GrantFiled: April 21, 2023Date of Patent: October 8, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Mihir Shaileshbhai Doctor, Alexander J. Branover, Benjamin Tsien, Indrani Paul, Christopher T. Weaver, Thomas J. Gibney, Stephen V. Kosonocky, John P. Petry
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Publication number: 20240329838Abstract: A data processing system includes a data processor having a memory controller, and a memory. The memory is coupled to the memory controller and is for reading and writing data synchronously with respect to a clock signal. The memory includes a sensor circuit that is responsive to a control signal to output a measured value without using the clock signal.Type: ApplicationFiled: March 31, 2023Publication date: October 3, 2024Applicant: Advanced Micro Devices, Inc.Inventor: Aaron D. Willey
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Publication number: 20240330045Abstract: A technique for scheduling executing items on a highly parallel processing architecture is provided. The technique includes identifying a plurality of execution items that share data, as indicated by having matching commonality metadata; identifying an execution unit for executing the plurality of execution items together; and scheduling the plurality of execution items for execution together on the execution unit.Type: ApplicationFiled: March 31, 2023Publication date: October 3, 2024Applicant: Advanced Micro Devices, Inc.Inventors: William Peter Ehrett, Vinay Bharadwaj Ramakrishnaiah, Bradford M. Beckmann
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Publication number: 20240330134Abstract: A system that includes at least a system memory, a chipset link, and a chipset attached memory is powered down. A boot-up process is loaded in the chipset attached memory. The boot-up process is performed for the system, via the chipset link, by the chipset attached memory. The boot-up process includes loading one or more memory testing applications. The system memory is tested using the one or more memory testing applications loaded by the chipset attached memory.Type: ApplicationFiled: March 27, 2023Publication date: October 3, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Jerry Anton Ahrens, William Robert Alverson, Joshua Taylor Knight, Amitabh Mehra, Anil Harwani, Grant Evan Ley
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Publication number: 20240329833Abstract: Techniques for performing memory operations are disclosed herein. The techniques include generating a plurality of performance log entries based on observed operations; generating a plurality of memory access log entries based on the observed operations, wherein each performance log entry of the plurality of performance log entries are associated with one or more memory access log entries of the plurality of memory access log entries, wherein each performance log entry is associated with an epoch; and wherein each memory access log entry is associated with an epoch and a memory address range.Type: ApplicationFiled: March 30, 2023Publication date: October 3, 2024Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Christopher J. Brennan, Akshay Lahiry, Guennadi Riguer
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Publication number: 20240330186Abstract: Cache directory lookup address augmentation techniques are described. In one example, a system includes a cache system including a plurality of cache levels and a cache coherence controller. The cache coherence controller is configured to perform a cache directory lookup using a cache directory. The cache directory lookup is configured to indicate whether data associated with a memory address specified by a memory request is valid in memory. The cache directory lookup is augmented to include an additional memory address based on the memory address.Type: ApplicationFiled: March 30, 2023Publication date: October 3, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Travis Henry Boraten, Varun Agrawal
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Publication number: 20240329135Abstract: A disclosed technique includes based on a clock pattern, determining an enable configuration for setting enable signals for one or more multi-cycle paths of a hardware logic network, setting the enable configuration for the one or more multi-cycle paths, and executing testing operations for the hardware logic network with the one or more multi-cycle paths enabled according to the enable configuration.Type: ApplicationFiled: March 31, 2023Publication date: October 3, 2024Applicant: Advanced Micro Devices, Inc.Inventor: James A. Wingfield
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Publication number: 20240333519Abstract: The disclosed computing device can include super flow control unit (flit) generation circuitry configured to generate a super flit containing two or more flits having two or more requests embedded therein, wherein the two or more requests have the same destination node identifiers and the super flit has a variable size based on a flit size and a number of existing requests in a source node that target a same destination node. The device can additionally include authentication circuitry configured to append a message authentication code to a last flit of the super flit. The device can also include communication circuitry configured to send the super flit to a network switch configured to route the super flit to a destination node corresponding to the same destination node identifiers. Various other methods, systems, and computer-readable media are also disclosed.Type: ApplicationFiled: March 31, 2023Publication date: October 3, 2024Applicant: Advanced Micro Devices, Inc.Inventors: SeyedMohammad SeyedzadehDelcheh, Sergey Blagodurov, Donald Matthews, Jr., Srilatha Manne
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Publication number: 20240329846Abstract: A memory sprint controller, responsive to an indicator of an irregular memory access phase, causes a memory controller to enter a sprint mode in which it temporarily adjusts at least one timing parameter of a dynamic random access memory (DRAM) to reduce a time in which a designated number of activate (ACT) commands are allowed to be dispatched to the DRAM.Type: ApplicationFiled: March 31, 2023Publication date: October 3, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Vignesh Adhinarayanan, Michael Ignatowski, Hyung-Dong Lee
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Publication number: 20240330076Abstract: Task allocation with chipset attached memory and additional processing unit is described. In accordance with the described techniques, a computing device includes a main system and one or more sub-systems which are coupled to the main system via a chipset link. The main system includes at least a processing unit and a system memory. The one or more sub-systems each include at least a chipset attached processing unit and a chipset attached memory. Contents of the system memory are transferable to the chipset attached memory of the sub-system via the chipset link to enable the chipset attached processing unit to perform the one or more tasks using the contents from the chipset attached memory.Type: ApplicationFiled: March 27, 2023Publication date: October 3, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Jerry Anton Ahrens, William Robert Alverson, Joshua Taylor Knight, Amitabh Mehra, Anil Harwani, Grant Evan Ley
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Publication number: 20240330198Abstract: Modifying memory page attributes using a programmable page attribute register of a core executing a process is described. In accordance with the described techniques, a host includes a core that is configured to generate a modified page table attribute for a page in system memory. The modified page table attribute represents at least one demoted permission for a page as specified by a system page table. The core is configured to maintain the modified page table attribute locally in the programmable page attribute register and execute at least one operation allocated to the page according to the modified page table attribute.Type: ApplicationFiled: March 30, 2023Publication date: October 3, 2024Applicant: Advanced Micro Devices, Inc.Inventor: Nuwan S. Jayasena
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Publication number: 20240331266Abstract: Devices and methods for rendering curves using ray tracing are provided which include tessellating a curve, representing at least a portion of an object in a scene, into a chain of capsules each comprising two spheres and a connecting cone, generating an acceleration structure comprising the chain of capsules, casting a ray in a space comprising the curve, and performing, for a capsule of the chain of capsules, a closed-form intersection test to render the curve. In a first example, the closed-form intersection test is performed using a single quadratic equation quadratic based on coefficients from input values of the two spheres. In a second example, the closed-form intersection test is performed based on an intersection between the ray and a blended sphere generated from a smallest distance between the ray and a centerline of the capsule and an offset.Type: ApplicationFiled: March 28, 2023Publication date: October 3, 2024Applicant: Advanced Micro Devices, Inc.Inventor: Trevor James Hedstrom
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Publication number: 20240329847Abstract: A memory sprint controller, responsive to an indicator of an irregular memory access phase, causes a memory controller to enter a sprint mode in which it temporarily adjusts at least one timing parameter of a dynamic random access memory (DRAM) to reduce a time in which a designated number of activate (ACT) commands are allowed to be dispatched to the DRAM.Type: ApplicationFiled: March 31, 2023Publication date: October 3, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Vignesh Adhinarayanan, Michael Ignatowski, Hyung-Dong Lee
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Patent number: 12107076Abstract: Integrated circuits and integrated circuit dies include TSVs laid out in symmetrical patterns. Because of the symmetrical arrangement of the TSVs and associated routing patterns, an integrated circuit is able to support operation of multiple similar dies that are placed in different positions in the integrated circuit. This in turn simplifies the design and production of the multiple similar dies, thus reducing development and manufacturing costs for the corresponding integrated circuits.Type: GrantFiled: December 28, 2021Date of Patent: October 1, 2024Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Wonjun Jung, Jasmeet Singh Narang, Tyrone Huang, Christopher Klement, Alan D. Smith, Edward Chang, John Wuu
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Patent number: 12105646Abstract: A system includes a memory implementing one or more virtual queues and a processor coupled to the memory. In response to issuing one or more requests for data, a processor maps one or more of the requests for data to a return queue structure. The processor then allocates one or more virtual queues to the return queue structure based on the mapped requests. In response to allocating the virtual queues to the return queue, the processor writes the data indicated in the mapped requests to the allotted virtual queues and enables the return queue for arbitration. When the return queue is enabled for arbitration, the processor reads out the data written to the allocated virtual queues, processes the read out data, and provides the processed data to a processing pipeline.Type: GrantFiled: December 1, 2021Date of Patent: October 1, 2024Assignee: Advanced Micro Devices, Inc.Inventor: Fataneh Ghodrat
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Patent number: 12107075Abstract: A chip for hybrid bonded interconnect bridging for chiplet integration, the chip comprising: a first chiplet; a second chiplet; an interconnecting die coupled to the first chiplet and the second chiplet through a hybrid bond.Type: GrantFiled: May 26, 2023Date of Patent: October 1, 2024Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Lei Fu, Brett P. Wilkerson, Rahul Agarwal
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Patent number: 12105139Abstract: A technique for operating a processing device is disclosed. The method includes irreversibly activating a testing mode switch of the processing device; in response to the activating, entering a testing mode in which normal operation of the processing device is disabled; receiving software for the processing device in the testing mode; based on whether the software is verified as testing mode-signed software, executing or not executing the software.Type: GrantFiled: December 29, 2021Date of Patent: October 1, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Vidyashankar Viswanathan, Richard E. George, Michael Y. Chow
