Patents Assigned to Advanced Micro Device, Inc.
  • Publication number: 20240402907
    Abstract: A technique for operating a memory system is disclosed. The technique includes performing a first request, by a first memory client, to access data at a first memory address, wherein the first memory address refers to data in a first memory section that is coupled to the first memory client via a direct memory connection; servicing the first request via the direct memory connection; performing a second request, by the first client, to access data at a second memory address, wherein the second memory address refers to data in a second memory section that is coupled to the first client via a cross connection; and servicing the second request via the cross connection.
    Type: Application
    Filed: August 14, 2024
    Publication date: December 5, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Vidyashankar Viswanathan, Richard E. George, Michael Y. Chow
  • Patent number: 12160238
    Abstract: Systems, apparatuses, and methods for implementing a low-power single-phase logic gate latch for clock-gating are disclosed. A latch circuit includes shared clocked transistors without including clock inverters. The shared clocked transistors include a P-type clocked transistor and an N-type clocked transistor, with the clock input coupled to the gate of the P-type clocked transistor and to the gate of the N-type clocked transistor. The P-type clocked transistor is coupled between first and second transistor stacks of the latch. The N-type clocked transistor is coupled to a source gate of a first stack N-type transistor gated by a data input and to a source gate of a second stack N-type transistor gated by the inverted data input. The latch has a lower clock pin capacitance than a traditional logic gate latch while also avoiding having clock inverters which reduces dynamic power consumption.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: December 3, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Nur Mohammad Baksh, Deepesh John
  • Patent number: 12159341
    Abstract: A technique for performing ray tracing operations is provided. The technique includes traversing through a bounding volume hierarchy to an instance node; performing an instance node transform using common circuitry; traversing to a leaf node of the bounding volume hierarchy; and performing an intersection test for the leaf node using the common circuitry.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: December 3, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Skyler Jonathon Saleh, Fataneh F. Ghodrat, Jeffrey Christopher Allan
  • Patent number: 12158845
    Abstract: Systems, apparatuses, and methods for maintaining region-based cache directories split between node and memory are disclosed. The system with multiple processing nodes includes cache directories split between the nodes and memory to help manage cache coherency among the nodes' cache subsystems. In order to reduce the number of entries in the cache directories, the cache directories track coherency on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. Each processing node includes a node-based cache directory to track regions which have at least one cache line cached in any cache subsystem in the node. The node-based cache directory includes a reference count field in each entry to track the aggregate number of cache lines that are cached per region. The memory-based cache directory includes entries for regions which have an entry stored in any node-based cache directory of the system.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: December 3, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Vydhyanathan Kalyanasundharam, Kevin M. Lepak, Amit P. Apte, Ganesh Balakrishnan
  • Patent number: 12158956
    Abstract: An apparatus and method for providing access to reliable boot firmware. In various implementations, a computing system includes an integrated circuit with a security processor. Prior to performing any steps of a bootup operation using one of multiple copies of boot firmware, the security processor determines whether multiple signatures exist where the signatures are based on the multiple copies of boot firmware. Each of the multiple copies of boot firmware is a copy of a particular version of boot firmware. If the multiple signatures do not yet exist, then the security processor generates the signatures using the multiple copies of boot firmware. During a bootup operation, when the security processor determines that the multiple signatures already exist, the security processor uses these signatures to validate one or more of the multiple copies of boot firmware. The security processor continues with the bootup operation using the validated copy of boot firmware.
    Type: Grant
    Filed: November 14, 2022
    Date of Patent: December 3, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Nimit Madhubhai Patel
  • Patent number: 12158827
    Abstract: A memory controller includes a command queue, an arbiter, and a controller. The controller is responsive to a repair signal for migrating data from a failing region of a memory to a buffer, generating at least one command to perform a post-package repair operation of the failing region, and migrating the data from the buffer to a substitute region of the memory. The controller migrates the data to and from the buffer by providing migration read requests and migration write requests, respectively, to the command queue. The arbiter uses the plurality of arbitration rules for both the read migration requests and the write migration requests, and the read access requests and the write access requests.
    Type: Grant
    Filed: December 29, 2022
    Date of Patent: December 3, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kedarnath Balakrishnan, Kevin M. Brandl, James R. Magro
  • Patent number: 12158842
    Abstract: A processing system allocates memory to co-locate input and output operands for operations for processing in memory (PIM) execution in the same PIM-local memory while exploiting row-buffer locality and complying with conventional memory abstraction. The processing system identifies as “super rows” virtual rows that span all the banks of a memory device. Each super row has a different bank-interleaving pattern, referred to as a “color”. A group of contiguous super rows that has the same PIM-interleaving pattern is referred to as a “color group”. The processing system assigns memory addresses to each operand (e.g., vector) of an operation for PIM execution to a super row having a different color within the same color group to co-locate the operands for each PIM execution unit and uses address hashing to alternate between banks assigned to elements of a first operand and elements of a second operand of the operation.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: December 3, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Benjamin Youngjae Cho, Armand Bahram Behroozi, Michael L. Chu, Ashwin Aji
  • Publication number: 20240393943
    Abstract: Generating optimization instructions for data processing pipelines is described. A pipeline optimization system computes resource usage information that describes memory and compute usage metrics during execution of each stage of the data processing pipeline. The system additionally generates data storage information that describes how data output by each pipeline stage is utilized by other stages of the pipeline. The pipeline optimization system then generates the optimization instructions to control how memory operations are performed for a specific data processing pipeline during execution. In implementations, the optimization instructions cause a memory system to discard data (e.g., invalidate cache entries) without copying the discarded data to another storage location after the data is no longer needed by the pipeline. The optimization instructions alternatively or additionally control at least one of evicting, writing-back, or prefetching data to minimize latency during pipeline execution.
    Type: Application
    Filed: August 5, 2024
    Publication date: November 28, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Harris Eleftherios Gasparakis
  • Publication number: 20240395295
    Abstract: A signal processing circuit includes an analog front-end circuit and a digital delay circuit. The analog circuit receives a clock signal and provides a compensated clock signal. The digital delay circuit is coupled to the analog front-end circuit and provides a compensated sample clock signal in response to delaying the compensated clock signal. The analog circuit measures a variation of a power supply voltage and adjusts a gain through the analog circuit according to a measured variation of the power supply voltage.
    Type: Application
    Filed: May 24, 2023
    Publication date: November 28, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Srikanth Reddy Gruddanti, Prasant Kumar Vallur, David Da-Wei Lin, Manoj N. Kulkarni, Priyadarshi Saxena
  • Patent number: 12153922
    Abstract: In accordance with described techniques for processing-in-memory (PIM) search stop control, a computing system or computing device includes a memory system that includes a stop condition check component, which receives an instruction that includes a programmed check value. The stop condition check component compares the programmed check value to outputs of a PIM component, and the stop condition check component initiates a stop instruction to stop the PIM component from processing subsequent computations based on an output of the PIM component matching the programmed check value.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: November 26, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Matthew R Poremba, Ersin Cukurtas
  • Patent number: 12154657
    Abstract: An arbiter is operable to pick commands from a command queue for dispatch to a memory. The arbiter includes a traffic throttle circuit for mitigating excess power usage increases in coordination with one or more additional arbiters. The traffic throttle circuit includes a monitoring circuit and a throttle circuit. The monitoring circuit is for measuring a number of read and write commands picked by the arbiter and the one or more additional arbiters over a first predetermined period of time. The throttle circuit, responsive to a low activity state, limits a number of read and write commands issued by the arbiter during a second predetermined period of time.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: November 26, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kedarnath Balakrishnan, James R. Magro
  • Patent number: 12153930
    Abstract: A processing device is provided which comprises memory configured to store data and a processor configured to execute a forward activation of the neural network using a low precision floating point (FP) format, scale up values of numbers represented by the low precision FP format and process the scaled up values of the numbers as non-zero values for the numbers. The processor is configured to scale up the values of one or more numbers, via scaling parameters, to a scaled up value equal to or greater than a floor of a dynamic range of the low precision FP format. The scaling parameters are, for example, static parameters or alternatively, parameters determined during execution of the neural network.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: November 26, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Hai Xiao
  • Patent number: 12154656
    Abstract: A receiver is trained for receiving a signal over a data bus. A volatile memory is commanded over the data bus to place a selected pulse-amplitude modulation (PAM) driver in a mode with a designated steady output level. At a receiver circuit coupled to the selected PAM driver, a respective reference voltage associated with the designated steady output level is swept through a range of voltages and the respective reference voltage is compared to a voltage received from the PAM driver to determine a respective voltage level received from the PAM driver.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: November 26, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Aaron D Willey, Karthik Gopalakrishnan, Pradeep Jayaraman
  • Patent number: 12154215
    Abstract: Devices and methods for node traversal for ray tracing are provided, which comprise casting a first ray in a space comprising objects represented by geometric shapes, traversing, for the first ray, at least one first node of an accelerated hierarchy structure representing an approximate volume of a group of the geometric shapes and a second node representing a volume of one of the geometric shapes, casting a second ray in the space, selecting, for the second ray, a starting node of traversal based on locations of intersection of the first ray and the second ray and an identifier which identifies one or more nodes intersected by the first ray and traversing, for the second ray, the accelerated hierarchy structure beginning at the starting node of traversal.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: November 26, 2024
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: David William John Pankratz, Konstantin I. Shkurko
  • Patent number: 12153487
    Abstract: The disclosed computer-implemented method includes receiving, by a first circuit subsystem, a hardware error signal and storing, in response to the hardware error signal, a signal state of the first circuit subsystem in a reset-persistent register. The method also includes sending, by the first circuit subsystem, the hardware error signal to a second circuit subsystem. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: December 16, 2022
    Date of Patent: November 26, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Tim Perley, Alexander Nozik, Siddharth K. Shah
  • Patent number: 12153524
    Abstract: A disclosed computing device includes at least one prefetcher and a processing device communicatively coupled to the prefetcher. The processing device is configured to detect a throttling instruction that indicates a start of a throttling region. The computing device is further configured to prevent the prefetcher from being trained on one or more memory instructions included in the throttling region in response to the throttling instruction. Various other apparatuses, systems, and methods are also disclosed.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: November 26, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John Kalamatianos, Marko Scrbak, Gabriel H. Loh, Akhil Arunkumar
  • Patent number: 12153958
    Abstract: Systems, apparatuses, and methods for abstracting tasks in virtual memory identifier (VMID) containers are disclosed. A processor coupled to a memory executes a plurality of concurrent tasks including a first task. Responsive to detecting one or more instructions of the first task which correspond to a first operation, the processor retrieves a first identifier (ID) which is used to uniquely identify the first task, wherein the first ID is transparent to the first task. Then, the processor maps the first ID to a second ID and/or a third ID. The processor completes the first operation by using the second ID and/or the third ID to identify the first task to at least a first data structure. In one implementation, the first operation is a memory access operation and the first data structure is a set of page tables. Also, in one implementation, the second ID identifies a first application of the first task and the third ID identifies a first operating system (OS) of the first task.
    Type: Grant
    Filed: October 7, 2022
    Date of Patent: November 26, 2024
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Anirudh R. Acharya, Michael J. Mantor, Rex Eldon McCrary, Anthony Asaro, Jeffrey Gongxian Cheng, Mark Fowler
  • Patent number: 12153957
    Abstract: A method for hierarchical work scheduling includes consuming a work item at a first scheduling domain having a local scheduler circuit and one or more workgroup processing elements. Consuming the work item produces a set of new work items. Subsequently, the local scheduler circuit distributes at least one new work item of the set of new work items to be executed locally at the first scheduling domain. If the local scheduler circuit of the first scheduling domain determines that the set of new work items includes one or more work items that would overload the first scheduling domain with work if scheduled for local execution, those work items are distributed to the next higher-level scheduler circuit in a scheduling domain hierarchy for redistribution to one or more other scheduling domains.
    Type: Grant
    Filed: September 30, 2022
    Date of Patent: November 26, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Matthaeus G. Chajdas, Christopher J. Brennan, Michael Mantor, Robert W. Martin, Nicolai Haehnle
  • Patent number: 12154224
    Abstract: Some implementations provide systems, devices, and methods for rendering a plurality of primitives of a frame, the plurality of primitives being divided into a plurality of batches of primitives and the frame being divided into a plurality of bins. For at least one batch of the plurality of batches the rendering includes, for each of the plurality of bins, rendering primitives of a first sub-batch rasterizing to that bin, and for each of the plurality of bins, rendering primitives of a second sub-batch rasterizing to that bin.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: November 26, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jan H. Achrenius, Kiia Kallio, Miikka Kangasluoma, Ruijin Wu, Anirudh R. Acharya
  • Publication number: 20240385872
    Abstract: In accordance with the described techniques for aggregation and scheduling of accelerator executable tasks, an accelerator device includes a processing element array and a command processor to receive a plurality of fibers each including multiple tasks and dependencies between the multiple tasks. The command processor places a first fiber in a sleep pool based on a first task within the first fiber having an unresolved dependency, and the command processor further places a second fiber in a ready pool based on a second task within the second fiber having a resolved dependency. Based on the second fiber being in the ready pool, the command processor launches the second task to be executed by the processing element array.
    Type: Application
    Filed: May 18, 2023
    Publication date: November 21, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Martha Massee Barker, Anthony Thomas Gutierrez, Mark Unruh Wyse, Ali Arda Eker