Patents Assigned to Advanced Micro Device, Inc.
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Publication number: 20240205093Abstract: The disclosed device includes a collective engine that can select a communication cost model from multiple communication cost models for a collective operation and configure a topology of a collective network for performing the collective operation using the selected communication cost model. Various other methods, systems, and computer-readable media are also disclosed.Type: ApplicationFiled: December 14, 2023Publication date: June 20, 2024Applicant: Advanced Micro Devices, Inc.Inventor: Josiah I. Clark
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Publication number: 20240201777Abstract: The disclosed method includes observing a utilization of a target sub-component of a functional unit of a processor using a control circuit coupled to the target sub-component. The method also includes detecting that the utilization is outside a desired utilization range and throttling one or more sub-components of the functional unit to reduce a power consumption of the functional unit. Various other methods, systems, and computer-readable media are also disclosed.Type: ApplicationFiled: December 19, 2022Publication date: June 20, 2024Applicant: Advanced Micro Devices, Inc.Inventors: James Mossman, Robert Cohen, Sudherssen Kalaiselvan, Tzu-Wei Lin
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Publication number: 20240203032Abstract: A technique for performing ray tracing operations is provided. The technique includes identifying triangles to include in a compressed triangle block; storing data common to the identified triangles as common data of the compressed triangle block; and storing data unique to the identified triangles as unique data of the compressed triangle block.Type: ApplicationFiled: December 14, 2022Publication date: June 20, 2024Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: David William John Pankratz, David Ronald Oldcorn, Daniel James Skinner, Michael John Livesley, David Kirk McAllister
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Publication number: 20240202047Abstract: The disclosed computer-implemented method can include reaching, by a chiplet involved in carrying out an operation for a process, a synchronization barrier. The method can additionally include receiving, by the chiplet, dedicated control messages pushed to the chiplet by other chiplets involved in carrying out the operation for the process, wherein the dedicated control messages are pushed over a control network by the other chiplets. The method can also include advancing, by the chiplet, the synchronization barrier in response to receipt of the dedicated control messages. Various other methods, systems, and computer-readable media are also disclosed.Type: ApplicationFiled: December 16, 2022Publication date: June 20, 2024Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Joseph L. Greathouse, Alan D. Smith, Anthony Asaro, Kostantinos Danny Christidis, Alexander Fuad Ashkar, Milind N. Nemlekar
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Publication number: 20240202116Abstract: An entry of a last level cache shadow tag array to track pending last level cache misses to private data in a previous level cache (e.g., an L2 cache), that also are misses to an exclusive last level cache (e.g., an L3 cache) and to the last level cache shadow tag array. Accordingly, last level cache miss status holding registers need not be expended to track cache misses to private data that are already being tracked by a previous level cache miss status holding register. Additionally or alternatively, up to a threshold number of last level cache pending misses to the same shared data from different processor cores are tracked in the last level cache shadow tag array, and any additional last level cache pending misses are tracked in a last level cache miss status holding register.Type: ApplicationFiled: December 20, 2022Publication date: June 20, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Jagadish B. Kotra, John Kalamatianos, Paul James Moyer, Nicholas Dean Lance, Sriram Srinivasan, Patrick James Shyvers, William Louie Walker
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Publication number: 20240202862Abstract: A processing device and a method of auto-tiled workload processing is provided. The processing device includes memory and a processor. The processor is configured to store instructions for operations to be executed on an image to be divided into a plurality of tiles, store information associated with the operations, select one of the operations for execution and execute an auto-tiling plan for the operation based on the information associated with the operations. The auto-tiling plan comprises, for example, determining a number of tiles used to divide the image and determining a size of one or more of the tiles of the image.Type: ApplicationFiled: December 20, 2022Publication date: June 20, 2024Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Guennadi Riguer, Mark Satterthwaite, Jeremy Lukacs, Zhuo Chen, Gareth Havard Thomas
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Publication number: 20240205092Abstract: The disclosed device includes a collective engine that can receive state information from nodes of a collective network. The collective engine can use the state information to initialize a topology of appropriate data routes between the nodes for the collective operation. Various other methods, systems, and computer-readable media are also disclosed.Type: ApplicationFiled: December 14, 2023Publication date: June 20, 2024Applicant: Advanced Micro Devices, Inc.Inventor: Josiah I. Clark
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Publication number: 20240205133Abstract: The disclosed device can perform a collective operation on received datasets, and split the result into chunks in accordance with a chunking scheme. The device can also forward the chunks in accordance with a routing scheme that can direct chunks to appropriate nodes of a collective network. Various other methods, systems, and computer-readable media are also disclosed.Type: ApplicationFiled: December 14, 2023Publication date: June 20, 2024Applicant: Advanced Micro Devices, Inc.Inventor: Josiah I. Clark
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Publication number: 20240203033Abstract: A technique for performing ray tracing operations is provided. The technique includes, in a first iteration of a ray traversal technique, traversing to an instance node of a bounding volume hierarchy; in a second iteration of the ray traversal technique that is subsequent to the first iteration, transforming a ray based on an instance transform of the instance node to generate a transformed ray; and in the second iteration, performing a ray-box intersection test for box node data of the instance node based on the transformed ray.Type: ApplicationFiled: December 14, 2022Publication date: June 20, 2024Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: David William John Pankratz, David Kirk McAllister, David Ronald Oldcorn, Michael John Livesley, Daniel James Skinner
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Publication number: 20240202121Abstract: Programmable data storage memory hierarchy techniques are described. In one example, a data storage system includes a memory hierarchy and a data movement controller. The memory hierarchy includes a hierarchical arrangement of a plurality of memory buffers. The data movement controller is configured to receive a data movement command and control data movement between the plurality of memory buffers based on the data movement command.Type: ApplicationFiled: December 20, 2022Publication date: June 20, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Shaizeen Dilawarhusen Aga, Johnathan Robert Alsop, Nuwan S Jayasena
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Publication number: 20240202144Abstract: A coherent memory fabric includes a plurality of coherent master controllers and a coherent slave controller. The plurality of coherent master controllers each include a response data buffer. The coherent slave controller is coupled to the plurality of coherent master controllers. The coherent slave controller, responsive to determining a selected coherent block read command is guaranteed to have only one data response, sends a target request globally ordered message to the selected coherent master controller and transmits responsive data. The selected coherent master controller, responsive to receiving the target request globally ordered message, blocks any coherent probes to an address associated with the selected coherent block read command until receipt of the responsive data is acknowledged by a requesting client.Type: ApplicationFiled: January 11, 2024Publication date: June 20, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Vydhyanathan Kalyanasundharam, Amit P. Apte, Eric Christopher Morton, Ganesh Balakrishnan, Ann M. Ling
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Publication number: 20240203034Abstract: A technique for performing ray tracing operations is provided. The technique includes, testing a plurality of bounding boxes for intersection with a ray in parallel, wherein the plurality of bounding boxes are specified by a plurality of box data items of a parent box node of a bounding volume hierarchy; determining that, for a first child node that is pointed to by a two or more node pointers specified by two or more box data items of the plurality of box data items, at least one bounding box specified by the two or more box data items is intersected by the ray; and in response to the determining, traversing to the first child node.Type: ApplicationFiled: December 14, 2022Publication date: June 20, 2024Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: David William John Pankratz, David Kirk McAllister, Daniel James Skinner, Michael John Livesley, David Ronald Oldcorn
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Publication number: 20240203036Abstract: A technique for building a bounding volume hierarchy is disclosed. The technique subdividing a candidate box node based on a resolution to generate a plurality of cells of the candidate box node; identifying a plurality of nodes of a triangle set collection that fit within the cells; generating a plurality of candidate splits based on the plurality of nodes; selecting a candidate split based on a selection criterion to obtain a selected candidate split; and generating child box nodes for a box node of a bounding volume hierarchy under construction, based on the selected candidate split.Type: ApplicationFiled: December 16, 2022Publication date: June 20, 2024Applicant: Advanced Micro Devices, Inc.Inventor: John Alexandre Tsakok
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Publication number: 20240201993Abstract: Data evaluation using processing-in-memory is described. In accordance with the described techniques, data evaluation logic is loaded into a processing-in-memory component. The processing-in-memory component executes the data evaluation logic to evaluate a minimum number of bits required to retrieve data from, or store data to, at least one memory location. A result is output indicating the number of bits required to represent data at the at least one memory location based on the evaluation.Type: ApplicationFiled: December 16, 2022Publication date: June 20, 2024Applicant: Advanced Micro Devices, Inc.Inventors: Shaizeen Dilawarhusen Aga, Leopold Grinberg
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Patent number: 12013752Abstract: A processing system includes a processing device coupled to a memory configured to check for and correct faults in requested data. In response to correcting the faults of the requested data, the memory sends the corrected data and unused check bits to the processing device as a plurality of fetch returns. The memory also sends a parity fetch based on the corrected data and one or more operations to the processing device. After receiving the plurality of fetch returns and the unused check bits, the processing device checks each fetch return for faults based on the unused check bits. In response to determining that a fetch return includes a fault, the processing device erases the fetch return and reconstructs the fetch return based on one or more other received fetch returns and the parity fetch.Type: GrantFiled: June 16, 2022Date of Patent: June 18, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Sudhanva Gurumurthi, Vilas Sridharan
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Patent number: 12014527Abstract: Methods, devices, and systems for compressing and decompressing a stream of indices associated with graphics primitives. A group of delta values is determined based on a group of indices of the stream of indices. The group of delta values is compared to delta values in a lookup table. The group of indices is compressed based on an entry in the lookup table if the group of delta values matches all delta values in the entry, otherwise, the group of indices is compressed based on variable-length encoding.Type: GrantFiled: February 26, 2021Date of Patent: June 18, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Kiia Kallio, Mika Tuomi, Ruijin Wu, Anirudh R. Acharya
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Patent number: 12014442Abstract: A primary processing unit includes queues configured to store commands prior to execution in corresponding pipelines. The primary processing unit also includes a first table configured to store entries indicating dependencies between commands that are to be executed on different ones of a plurality of processing units that include the primary processing unit and one or more secondary processing units. The primary processing unit also includes a scheduler configured to release commands in response to resolution of the dependencies. In some cases, a first one of the secondary processing units schedules the first command for execution in response to resolution of a dependency on a second command executing in a second one of the secondary processing units. The second one of the secondary processing units notifies the primary processing unit in response to completing execution of the second command.Type: GrantFiled: December 19, 2019Date of Patent: June 18, 2024Assignee: Advanced Micro Devices, Inc.Inventor: Rex Eldon McCrary
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Patent number: 12014208Abstract: Techniques for executing shader programs with divergent control flow on a single instruction multiple data (“SIMD”) processor are disclosed. These techniques includes detecting entry into a divergent section of a shader program and, for the work-items that enter the divergent section, placing a task entry into a task queue associated with the target of each work-item. The target is the destination, in code, of any particular work-item, and is also referred to as a code segment herein. The task queues store task entries for code segments generated by different (or the same) wavefronts. A command processor examines task lists and schedules wavefronts for execution by grouping together tasks in the same task list into wavefronts and launching those wavefronts. By grouping tasks from different wavefronts together for execution in the same front, serialization of execution is greatly reduced or eliminated.Type: GrantFiled: June 29, 2018Date of Patent: June 18, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Skyler Jonathon Saleh, Maxim V. Kazakov
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Patent number: 12014213Abstract: A method of operating a computing system includes storing a memory map identifying a first physical memory address as associated with a high performance memory and identifying a second physical memory address as associated with a low power consumption memory, servicing a first memory access request received from an application by accessing application data at the first physical memory address, in response to a change in one or more operating conditions of the computing system, moving the application data between the first physical memory address and the second physical memory address based on the memory map, and servicing a second memory access request received from the application by accessing the application data at the second physical memory address.Type: GrantFiled: September 9, 2019Date of Patent: June 18, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Sonu Arora, Daniel L. Bouvier
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Patent number: 12013810Abstract: A semiconductor module comprises multiple non-homogeneous semiconductor dies disposed on the semiconductor module, with each semiconductor die having a set of circuitry modules that are common to all of the semiconductor dies and also a set of supporting circuitry modules that are distinct between the semiconductor dies. An interconnect communicatively couples the semiconductor dies together. Commands for processing by the semiconductor module may be routed to individual semiconductor dies based on capabilities of the particular circuitry modules disposed on those individual semiconductor dies.Type: GrantFiled: September 29, 2022Date of Patent: June 18, 2024Assignee: Advanced Micro Devices, Inc.Inventor: Matthaeus G. Chajdas
