Patents Assigned to Advanced Micro Device, Inc.
  • Publication number: 20240220247
    Abstract: Permute instructions for register-based lookups is described. In accordance with the described techniques, a processor is configured to perform a register-based lookup by retrieving a first result from a first lookup table based on a subset of bits included in an index of a destination register, retrieving a second result from a second lookup table based on the subset of bits included in the index of the destination register, selecting the first result or the second result based on a bit in the index of the destination register that is excluded from the subset of bits, and overwriting data included in the index of the destination register using a selected one of the first result or the second result.
    Type: Application
    Filed: December 30, 2022
    Publication date: July 4, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Vadim Vadimovich Nikiforov, Yasuko Eckert, Bradford Michael Beckmann
  • Publication number: 20240220336
    Abstract: In accordance with described techniques for PE-centric all-to-all communication, a distributed computing system includes processing elements, such as graphics processing units, distributed in clusters. An all-to-all communication procedure is performed by the processing elements that are each configured to generate data packets in parallel for all-to-all data communication between the clusters. The all-to-all communication procedure includes a first stage of intra-cluster parallel data communication between respective processing elements of each of the clusters; a second stage of inter-cluster data exchange for all-to-all data communication between the clusters; and a third stage of intra-cluster data distribution to the respective processing elements of each of the clusters.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Kishore Punniyamurthy, Khaled Hamidouche, Brandon K Potter, Rohit Shahaji Zambre
  • Patent number: 12026401
    Abstract: In accordance with described techniques for DRAM row management for processing in memory, a plurality of instructions are obtained for execution by a processing in memory component embedded in a dynamic random access memory. An instruction is identified that last accesses a row of the dynamic random access memory, and a subsequent instruction is identified that first accesses an additional row of the dynamic random access memory. A first command is issued to close the row and a second command is issued to open the additional row after the row is last accessed by the instruction.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: July 2, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Niti Madan, Yasuko Eckert, Varun Agrawal, John Kalamatianos
  • Patent number: 12026380
    Abstract: A processing system including a parallel processing unit selectively allocating pages of memory for interleaving across configurable subsets of channels based on a mode of allocation. In some embodiments, in a first mode, a page of memory is allocated to and interleaved across a plurality of channels, and in a second mode, a page of memory is allocated to and interleaved across a subset of the plurality of channels.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: July 2, 2024
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Mark Fowler, Anthony Asaro, Vydhyanathan Kalyanasundharam
  • Patent number: 12026099
    Abstract: A cache stores, along with data that is being transferred from a higher level cache to a lower level cache, information indicating the higher level cache location from which the data was transferred. Upon receiving a request for data that is stored at the location in the higher level cache, a cache controller stores the higher level cache location information in a status tag of the data. The cache controller then transfers the data with the status tag indicating the higher level cache location to a lower level cache. When the data is subsequently updated or evicted from the lower level cache, the cache controller reads the status tag location information and transfers the data back to the location in the higher level cache from which it was originally transferred.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: July 2, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Paul James Moyer
  • Patent number: 12026080
    Abstract: Systems and methods for building applications by automatically incorporating application performance data into the application build process are disclosed. By capturing build settings and performance data from prior applications being executed on different computing systems such as bare metal and virtualized cloud instances, a performance database may be maintained and used to predict build settings that improve application performance (e.g., on a specific computing system or computing system configuration).
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: July 2, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Max Alt, Paulo Roberto Pereira de Souza filho
  • Patent number: 12028190
    Abstract: A driver circuit includes a feed-forward equalization (FFE) circuit. The FFE circuit receives a plurality of pulse-amplitude modulation (PAM) symbol values to be transmitted at one of multiple PAM levels. The FFE circuit includes a first partial lookup table, one or more additional partial lookup tables, and an adder circuit. The first partial lookup table contains partial finite impulse-response (FIR) values and indexed based on a current PAM symbol value, a precursor PAM symbol value, and a postcursor PAM symbol value. The one or more additional partial lookup tables each contain partial FIR values and indexed based on a respective additional one or more of the PAM symbol values. The adder circuit adds results of lookups from the first partial lookup table and the additional partial lookup tables to produce an output value.
    Type: Grant
    Filed: December 22, 2022
    Date of Patent: July 2, 2024
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Pradeep Jayaraman, Karthik Gopalakrishnan, Andrew Egli
  • Patent number: 12026387
    Abstract: A page swapping memory protection system tracks accesses to physical memory pages, such as in a table with each row storing a physical memory page address and a counter value. This counter value records the number of accesses (e.g., read access or write accesses) to the corresponding physical memory page. In response to one of the counters exceeding a threshold value, the corresponding physical memory page is swapped with another page in physical memory (e.g., a page the table indicates has a smallest number of accesses). According, unreliability in the physical memory introduced due to frequent accesses to a particular physical memory page is mitigated.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: July 2, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Seyedmohammad SeyedzadehDelcheh, Sriseshan Srikanth
  • Publication number: 20240211402
    Abstract: In accordance with the described techniques for condensed coherence directory entries for processing in memory, a computing device includes a core that includes a cache, a memory that includes multiple banks, a coherence directory that includes a condensed entry indicating that data associated with a memory address and the multiple banks is not stored in the cache, and a cache coherence controller. The cache coherence controller receives a processing-in-memory command to the memory address and performs a single lookup in the coherence directory for the processing-in-memory command based on inclusion of the condensed entry in the coherence directory.
    Type: Application
    Filed: December 27, 2022
    Publication date: June 27, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Travis Henry Boraten, Varun Agrawal, Michael Warren Boyer
  • Publication number: 20240211407
    Abstract: A memory request issue counter (MRIC) is maintained that is incremented for every memory access a central processing unit core makes. A region reuse distance table is also maintained that includes multiple entries each of which stores the region reuse distance for a corresponding region. When a memory access request for a physical address is received, a reuse distance for the physical address is calculated. This reuse distance is the difference between the current MRIC value and a previous MRIC value for the physical address. The previous MRIC value for the physical address is the MRIC value the MRIC had when a memory access request for the physical address was last received. A region reuse distance for a region that includes the physical address is generated based on the reuse distance for the physical address and used to manage the cache.
    Type: Application
    Filed: December 27, 2022
    Publication date: June 27, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: John Kalamatianos, Jagadish B. Kotra, Asmita Pal
  • Publication number: 20240211416
    Abstract: Physical adjustment to system memory with chipset attached memory is described. In accordance with the described techniques, an indication for making one or more physical adjustments to system memory of a device is received. Contents of the system memory are transferred via a chipset link to a chipset attached memory. The device is operated using the contents from the chipset attached memory while the one or more physical adjustments are made to adjust the system memory. After the one or more physical adjustments, the contents are transferred back from the chipset attached memory to the adjusted system memory via the chipset link.
    Type: Application
    Filed: December 27, 2022
    Publication date: June 27, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Jerry Anton Ahrens, William Robert Alverson, Joshua Taylor Knight, Amitabh Mehra, Anil Harwani, Grant Evan Ley
  • Publication number: 20240212259
    Abstract: An implementation comprises traversing a bounding volume hierarchy for each ray of a plurality of rays concurrently using a plurality of execution items. In response to determining that a first execution item of the plurality of execution items is finished traversing the bounding volume hierarchy for a first ray of the plurality rays, the embodiment causes the first execution item to traverse the bounding volume hierarchy for a second ray of the plurality of rays while a second execution item of the plurality of execution items traverses the bounding volume hierarchy for the second ray. And the embodiment comprises initiating side-effects with the first and second execution items in an order indicated by the bounding volume hierarchy.
    Type: Application
    Filed: December 27, 2022
    Publication date: June 27, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: David William John Pankratz, Daniel James Skinner, Michael John Livesley
  • Publication number: 20240212908
    Abstract: The disclosed inductor includes a magnetic material surrounding a conductive core. The magnetic material and conductive core can be embedded in a substrate. The magnetic material and conductive core can be formed in the substrate, using a magnetic composite material. Various other systems and methods are also disclosed.
    Type: Application
    Filed: September 29, 2023
    Publication date: June 27, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Robert Grant Spurney, Alexander Helmut Pfeiffenberger, Sri Ranga Sai Boyapati, Deepak Vasant Kulkarni
  • Publication number: 20240211142
    Abstract: Extended training for memory is described. In accordance with the described techniques, a training request to train a memory with extended training is received. The extended training corresponds to a longer amount of time than a default training. The extended training of the memory is performed using a set of target memory settings. In one or more implementations, the extended training is performed during a boot up phase of the computing device.
    Type: Application
    Filed: December 27, 2022
    Publication date: June 27, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Alicia Wen Ju Yurie Leong, Jayesh Hari Joshi, William Robert Alverson, Joshua Taylor Knight, Jerry Anton Ahrens, Amitabh Mehra, Grant Evan Ley
  • Publication number: 20240211173
    Abstract: A memory controller includes an arbiter. The arbiter is configured to elevate a priority of memory access requests that generate row activate commands in response to receiving a same-bank refresh request, and to send a same-bank refresh command in response to receiving the same-bank refresh request.
    Type: Application
    Filed: December 22, 2022
    Publication date: June 27, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Kedarnath Balakrishnan, Jing Wang, Guanhao Shen
  • Publication number: 20240211393
    Abstract: In accordance with the described techniques for leveraging processing in memory registers as victim buffers, a computing device includes a memory, a processing in memory component having registers for data storage, and a memory controller having a victim address table that includes at least one address of a row of the memory that is stored in the registers. The memory controller receives a request to access the row of the memory and accesses data of the row from the registers based on the address of the row being included in the victim address table.
    Type: Application
    Filed: December 27, 2022
    Publication date: June 27, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Jagadish B Kotra, Dong Kai Wang
  • Publication number: 20240211362
    Abstract: An exemplary system includes and/or represents an agent and a machine check architecture. In one example, the machine check architecture includes and/or represents at least one circuit configured to report errors via at least one reporting register. In this example, the machine check architecture also includes and/or represents at least one error-injection register configured to cause the circuit to inject at least one fabricated error report into the reporting register in response to a write operation performed by the agent on at least one bit of the error-injection register. Various other devices, systems, and methods are also disclosed.
    Type: Application
    Filed: December 27, 2022
    Publication date: June 27, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Vilas Sridharan, Hanbing Liu, Francisco L. Duran
  • Publication number: 20240211134
    Abstract: A memory controller includes an arbiter, a vector arithmetic logic unit (VALU), a read buffer and a write buffer both coupled to the VALU, and an atomic memory operation scheduler. The VALU performs scattered atomic memory operations on arrays of data elements responsive to selected memory access commands. The atomic memory operation scheduler is for scheduling atomic memory operations at the VALU; identifying a plurality of scattered atomic memory operations with commutative and associative properties, the plurality of scattered atomic memory operations on at least one element of an array of data elements associated with an address; and commanding the VALU to perform the plurality of scattered atomic memory operations.
    Type: Application
    Filed: December 23, 2022
    Publication date: June 27, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventors: John Kalamatianos, Karthik Ramu Sangaiah, Anthony Thomas Gutierrez
  • Publication number: 20240212777
    Abstract: Memory verification using processing-in-memory is described. In accordance with the described techniques, memory testing logic is loaded into a processing-in-memory component. The processing-in-memory component executes the memory testing logic to test a memory. An indication is output of a detected fault in the memory based on testing the memory.
    Type: Application
    Filed: December 27, 2022
    Publication date: June 27, 2024
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Robin Conradine Knauerhase
  • Publication number: 20240214246
    Abstract: A driver circuit includes a feed-forward equalization (FFE) circuit. The FFE circuit receives a plurality of pulse-amplitude modulation (PAM) symbol values to be transmitted at one of multiple PAM levels. The FFE circuit includes a first partial lookup table, one or more additional partial lookup tables, and an adder circuit. The first partial lookup table contains partial finite impulse-response (FIR) values and indexed based on a current PAM symbol value, a precursor PAM symbol value, and a postcursor PAM symbol value. The one or more additional partial lookup tables each contain partial FIR values and indexed based on a respective additional one or more of the PAM symbol values. The adder circuit adds results of lookups from the first partial lookup table and the additional partial lookup tables to produce an output value.
    Type: Application
    Filed: December 22, 2022
    Publication date: June 27, 2024
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Pradeep Jayaraman, Karthik Gopalakrishnan, Andrew Egli