Abstract: Various circuit boards with mounted passive components and method of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes at least partially encapsulating a first plurality of passive components in a molding material to create a first molded passive component group. The first molded passive component group is mounted on a surface of a circuit board. The first plurality of passive components are electrically connected to the circuit board.

Abstract: Data transmission mitigating interwire crosstalk including: dividing a data block to be transmitted from a transmitter to a receiver across a set of signal wires into sub-blocks; encoding each of the sub-blocks into a plurality of codewords; selecting, for each sub-block by a cost function, one of the codewords that is less likely to introduce interwire crosstalk; transmitting the selected codewords; and updating the cost function at the transmitter with feedback from the receiver.

Abstract: Methods and apparatus provide virtual to physical address translations and a hardware page table walker with region based page table prefetch operation that produces virtual memory region tracking information that includes at least: data representing a virtual base address of a virtual memory region and a physical address of a first page table entry (PTE) corresponding to a virtual page within the virtual memory region. The hardware page table walker, in response to the TLB miss indication, prefetches a physical address of a second page table entry, that provides a final physical address for the missed TLB entry, using the virtual memory region tracking information. In some implementations, the prefetching of the physical PTE address is done in parallel with earlier levels of a page walk operations.

Abstract: A system and method for detecting and measuring electrostatic discharge during semiconductor assembly are described. A semiconductor device fabrication process forms a conductor between two metal routes in a series path on a semiconductor die. The series path is between a bump on the die and a substrate tie. The two metal routes have a width greater than a threshold based on a metal width capable of conducting a critical current density caused by an electrostatic discharge event without conductive failure or breakdown. The conductor has a width less than the threshold. When an electrostatic discharge event occurs, if the current exceeds a critical amount of current, the conductor experiences conductive breakdown and current ceases to flow. During later testing, this series path is tested for open connections, which indicate whether the conductor acting as an electrical on-die fuse experienced conductive failure during assembly of a semiconductor chip.

Abstract: Memory management circuitry and processes operate to improve reliability of a group of memory stacks, providing that if a memory stack or a portion thereof fails during the product's lifetime, the system may still recover with no errors or data loss. A front-end controller receives a block of data requested to be written to memory, divides the block into sub-blocks, and creates a new redundant reliability sub-block. The sub-blocks are then written to different memory stacks. When reading data from the memory stacks, the front-end controller detects errors indicating a failure within one of the memory stacks, and recovers corrected data using the reliability sub-block. The front-end controller may monitor errors for signs of a stack failure and disable the failed stack.

Abstract: Systems, apparatuses, and methods for implementing automatic data format detection techniques are disclosed. A graphics engine receives data of indeterminate format and the graphics engine predicts an organization of the data. As part of the prediction, the graphics engine predicts the pixel depth (i.e., bytes per pixel (BPP)) and format separately. The graphics engine folds the data along pixel and channel boundaries to help in determining the pixel depth and format. The graphics engine scores modes against each other to generate different predictions for different formats. Then, the graphics engine generates scores for the predictions to determine which mode has a highest correlation with the input data. Next, the graphics engine chooses the format which attains the best score among the scores that were generated for the different modes. Then, the graphics engine compresses the unknown data using the chosen format with the best score.

Abstract: An integrated circuit device wafer includes a silicon wafer substrate and a back side metallization structure. The back side metallization structure includes a first adhesion layer on the back side of the substrate, a first metal later over the first adhesion layer, a second metal layer over the first metal layer, and a second adhesion layer over the second metal layer. The first includes at least one of: silicon nitride and silicon dioxide. The first metal layer includes titanium. The second metal layer includes nickel. The second adhesion layer includes at least one of: silver, gold, and tin. An indium preform is placed between the second adhesion layer and the lid and the indium preform is reflowed.

Abstract: Wavefront loading in a processor is managed and includes monitoring a selected wavefront of a set of wavefronts. Reuse of memory access requests for the selected wavefront is counted. A cache hit rate in one or more caches of the processor is determined based on the counted reuse. Based on the cache hit rate, subsequent memory requests of other wavefronts of the set of wavefronts are modified by including a type of reuse of cache lines in requests to the caches. In the caches, storage of data in the caches is based on the type of reuse indicated by the subsequent memory access requests. Reused cache lines are protected by preventing cache line contents from being replaced by another cache line for a duration of processing the set of wavefronts. Caches are bypassed when streaming access requests are made.

Abstract: Techniques are provided herein for pre-emptively reinforcing one or more buses of a computing device against the effects of signal noise that could cause a reduction in signal integrity. The techniques generally include detecting an event (or “trigger”) that would tend to indicate that a reduction in signal integrity will occur, examining a reinforcement action policy and system status to determine what reinforcement action to take, and performing the reinforcement action.

Abstract: A method includes adding a set of one or more victim rows to a first probabilistic filter and to a second probabilistic filter, in response to a memory access request, identifying a candidate victim row adjacent to a memory address specified by a memory access request, identifying the candidate victim row as a victim row in the set of victim rows based on performing a lookup of the candidate victim row in a selected filter, where the selected filter includes one of the first probabilistic filter and the second probabilistic filter, in response to identifying the candidate row as the victim row, enabling a row hammering countermeasure, clearing the first probabilistic filter in each of a first set of time periods, and clearing the second probabilistic filter in each of a second set of time periods interleaved with the first set of time periods.

Abstract: A data fabric routes requests between the plurality of requestors and the plurality of responders. The data fabric includes a crossbar router, a coherent slave controller coupled to the crossbar router, and a probe filter coupled to the coherent slave controller and tracking the state of cached lines of memory. Power state control circuitry operates, responsive to detecting any of a plurality of designated conditions, to cause the probe filter to enter a retention low power state in which a clock signal to the probe filter is gated while power is maintained to the probe filter. Entering the retention low power state is performed when all in-process probe filter lookups are complete.

Abstract: Described herein is a technique for performing ray tracing. According to this technique, instead of executing intersection and/or any hit shaders during traversal of an acceleration structure to determine the closest hit for a ray, an acceleration structure is fully traversed in an invocation of a shader program, and the closest intersection with a triangle is recorded in a data structure associated with the material of the triangle. Later, a scheduler launches waves by grouping together multiple data items associated with the same material. The rays processed by that wave are processed with a continuation ray, rather than the full original ray. A continuation ray starts from the previous point of intersection and extends in the direction of the original ray. These steps help counter divergence that would occur if a single shader program that inlined the intersection and any hit shaders were executed.

Abstract: Approaches are provided for implementing hardware-software collaborative address mapping schemes that enable mapping data elements which are accessed together in the same row of one bank or over the same rows of different banks to achieve higher performance by reducing row conflicts. Using an intra-bank frame striping policy (IBFS), corresponding subsets of data elements are interleaved into a single row of a bank. Using an intra-channel frame striping policy (ICFS), corresponding subsets of data elements are interleaved into a single channel row of a channel. A memory controller utilizes ICFS and/or IBFS to efficiently store and access data elements in memory, such as processing-in-memory (PIM) enabled memory.

Abstract: Methods and systems are described. A system includes a redundant shader pipe array that performs rendering calculations on data provided thereto and a shader pipe array that includes a plurality of shader pipes, each of which performs rendering calculations on data provided thereto. The system also includes a circuit that identifies a defective shader pipe of the plurality of shader pipes in the shader pipe array. In response to identifying the defective shader pipe, the circuit generates a signal. The system also includes a redundant shader switch. The redundant shader switch receives the generated signal, and, in response to receiving the generated signal, transfers the data for the defective shader pipe to the redundant shader pipe array.

Abstract: Techniques for scheduling operations for a task graph on a processing device are provided. The techniques include receiving a task graph that specifies one or more passes, one or more resources, and one or more directed edges between passes and resources; identifying independent passes and dependent passes of the task graph; based on performance criteria of the processing device, scheduling commands to execute the passes; and transmitting scheduled commands to the processing device for execution as scheduled.

Abstract: Techniques for executing an atomic command in a distributed computing network are provided. A core cluster, including a plurality of processing cores that do not natively issue atomic commands to the distributed computing network, is coupled to a translation unit. To issue an atomic command, a core requests a location in the translation unit to write an opcode and operands for the atomic command. The translation unit identifies a location (a “window”) that is not in use by another atomic command and indicates the location to the processing core. The processing core writes the opcode and operands into the window and indicates to the translation unit that the atomic command is ready. The translation generates an atomic command and issues the command to the distributed computing network for execution. After execution, the distributed computing network provides a response to the translation unit, which provides that response to the core.

Abstract: Systems, apparatuses, and methods for implementing a dual-purpose millimeter-wave frequency band transmitter are disclosed. A system includes a dual-purpose transmitter sending a video stream over a wireless link to a receiver. In some embodiments, the video stream is generated as part of an augmented reality (AR) or virtual reality (VR) application. The transmitter operates in a first mode to scan and map an environment of the transmitter and receiver. The transmitter generates radio frequency (RF) signals in a first frequency range while operating in the first mode. Additionally, the transmitter operates in a second mode to send video data to the receiver, and the transmitter generates RF signals in the first frequency range while operating in the second mode.

Abstract: An electronic device that includes a controller functional block and a computational functional block having one or more computational elements performs operations associated with a training operation for a generative adversarial network, the generative adversarial network including a generative network and a discriminative network. The controller functional block determines one or more characteristics of the generative adversarial network. Based on the one or more characteristics, the controller functional block configures the one or more computational elements to perform processing operations for each of the generative network and the discriminative network during the training operation for the generative adversarial network.

Abstract: Described herein are techniques for performing ray tracing operations. A command processor executes custom instructions for orchestrating a ray tracing pipeline. The custom instructions cause the command processor to perform a series of loop iterations, each at a particular recursion depth. In a first loop iteration, a ray generation shader is executed that triggers execution of a trace ray operation. In any other iteration, zero or more shaders are executed based on the contents of a shader queue. Any shader may trigger execution of a trace ray operation. The trace ray operation determines whether a ray specified by the shader intersects a triangle. The ray trace operation places shader entries into a shader queue, at the current recursion depth plus 1. The command processor updates the current recursion depth based on whether a trace ray operation is executed. The loop ends when the recursion depth is less than a threshold.

Abstract: An electronic device includes a processor having a cache memory, a plurality of physical registers, and a promotion logic functional block. The promotion logic functional block promotes prefetched data from a portion of a cache block in the cache memory into a given physical register, the promoting including storing the prefetched data in the given physical register. Upon encountering a load micro-operation that loads data from the portion of the cache block into a destination physical register, the promotion logic functional block sets the processor so that the prefetched data stored in the given physical register is provided to micro-operations that depend on the load micro-operation.