Patents Assigned to Advanced Micro Device, Inc.
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Publication number: 20220317934Abstract: A memory controller includes a command queue that receives and stores decoded memory commands and information related thereto including information indicating a type, a priority, an age, and a region of a memory system for a corresponding decoded memory command, and an arbiter coupled to the command queue and picks selected decoded memory commands among the decoded memory commands from the command queue for dispatch to the memory system by comparing the priority and the age for decoded memory commands having a first type. The arbiter detects when the command queue receives a decoded memory command of a second type opposite to said first type that accesses a first memory region of the memory system, and in response performs at least one pre-work action that reduces a latency of the decoded memory command of the second type.Type: ApplicationFiled: September 30, 2021Publication date: October 6, 2022Applicant: Advanced Micro Devices, Inc.Inventors: Guanhao Shen, Ravindra Nath Bhargava
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Publication number: 20220317924Abstract: A memory controller includes a command queue that receives and stores decoded memory commands and information related thereto including information indicating a type, a priority, an age, and a region of a memory system for a corresponding decoded memory command, and an arbiter coupled to the command queue and picks selected decoded memory commands among the decoded memory commands from the command queue for dispatch to the memory system by comparing the priority and the age for decoded memory commands having a first type. The arbiter detects when the command queue receives a decoded memory command of a second type opposite to said first type that accesses a first memory region of the memory system, and in response elevates at least one of the priority and the age of a decoded command of the first type that accesses the first memory region already stored in the command queue.Type: ApplicationFiled: March 31, 2021Publication date: October 6, 2022Applicant: Advanced Micro Devices, Inc.Inventors: Guanhao Shen, Ravindra Nath Bhargava
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Publication number: 20220317755Abstract: A memory controller couples to a data fabric clock domain, and to a physical layer interface circuit PHY clock domain. A first interface circuit adapts transfers between the data fabric clock domain (FCLK) and the memory controllers clock domain, and a second interface circuit couples the memory controller to the PHY clock domain. A power controller responds to a power state change request by sending commands to the second interface circuit to change parameters of a memory system and to update a set of timing parameters of the memory controller according to a selected power state of a plurality of power states. The power controller further responds to a request to synchronize with a new frequency on the FCLK domain by changing a set of timing parameters of the clock interface circuit without changing the set of timing parameters of the memory system or the selected power state.Type: ApplicationFiled: March 31, 2021Publication date: October 6, 2022Applicant: Advanced Micro Devices, Inc.Inventors: James R. Magro, Christopher Weaver, Abhishek Kumar Verma
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Publication number: 20220319089Abstract: Techniques for executing computing work by a plurality of chiplets are provided. The techniques include assigning workgroups of a kernel dispatch packet to the chiplets; by each chiplet, executing the workgroups assigned to that chiplet; for each chiplet, upon completion of all workgroups assigned to that chiplet for the kernel dispatch packet, notifying the other chiplets of such completion; and upon completion of all workgroups of the kernel dispatch packet, notifying a client of such completion and proceeding to a subsequent kernel dispatch packet.Type: ApplicationFiled: March 31, 2021Publication date: October 6, 2022Applicant: Advanced Micro Devices, Inc.Inventors: Milind N. Nemlekar, Maxim V. Kazakov, Prerit Dak
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Publication number: 20220318161Abstract: A memory controller includes a command queue and an arbiter operating in a first voltage domain, and a physical layer interface (PHY) operating in a second voltage domain. The memory controller includes isolation cells operable to isolate the PHY from the first voltage domain. A local power state controller, in response to a first power state command, provides configuration and state data for storage in an on-chip RAM memory, causes the memory controller to enter a powered-down state, and maintains the PHY in a low-power state in which the second voltage domain is powered while the memory controller is in the powered-down state.Type: ApplicationFiled: March 31, 2021Publication date: October 6, 2022Applicant: Advanced Micro Devices, Inc.Inventors: Kevin M. Brandl, Indrani Paul, Jean J. Chittilappilly, Abhishek Kumar Verma, James R. Magro, Kavyashree Pilar
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Publication number: 20220319091Abstract: A method and apparatus of tile rendering of an image for a display in a computer system includes receiving the image in a graphics pipeline of the computer system, the image comprising one or more three dimensional (3D) objects. The image is divided into one or more tiles. A depth test is performed on the one or more tiles, and based upon the depth test, visibility information of the one or more tiles is binned.Type: ApplicationFiled: December 27, 2021Publication date: October 6, 2022Applicant: Advanced Micro Devices, Inc.Inventors: Mika Tuomi, Ruijin Wu, Anirudh R. Acharya
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Publication number: 20220317927Abstract: A data processor includes a fabric-attached memory (FAM) interface for coupling to a data fabric and fulfilling memory access instructions. A requestor-side adaptive consistency controller coupled to the FAM interface requests notifications from a fabric manager for the fabric-attached memory regarding changes in requestors authorized to access a FAM region which the data processor is authorized to access. If a notification indicates that more than one requestor is authorized to access the FAM region, fences are activated for selected memory access instructions in a local application.Type: ApplicationFiled: March 31, 2021Publication date: October 6, 2022Applicant: Advanced Micro Devices, Inc.Inventors: Sergey Blagodurov, Brandon K. Potter, Johnathan Alsop
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Publication number: 20220317928Abstract: A memory controller includes a command queue and an arbiter for selecting entries from the command queue for transmission to a DRAM. The arbiter transacts streaks of consecutive read commands and streaks of consecutive write commands. The arbiter transacts a streak for at least a minimum burst length based on a number of commands of a designated type available to be selected by the arbiter. Following the minimum burst length, the arbiter decides to start a new streak of commands of a different type based on a first set of one or more conditions indicating intra-burst efficiency.Type: ApplicationFiled: March 31, 2021Publication date: October 6, 2022Applicant: Advanced Micro Devices, Inc.Inventors: Guanhao Shen, Ravindra Nath Bhargava
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Publication number: 20220317923Abstract: A memory controller includes an arbiter for selecting memory requests from a command queue for transmission to a DRAM memory. The arbiter includes a bank group tracking circuit that tracks bank group numbers of three or more prior write requests selected by the arbiter. The arbiter also includes a selection circuit that selects requests to be issued from the command queue, and prevents selection of write requests and associated activate commands to the tracked bank group numbers unless no other write request is eligible in the command queue. The bank group tracking circuit indicates that a prior write request and associated activate commands are eligible to be issued after a number of clock cycles has passed corresponding to a minimum write-to-write timing period for the bank group of the prior write request.Type: ApplicationFiled: March 31, 2021Publication date: October 6, 2022Applicant: Advanced Micro Devices, Inc.Inventor: Kedarnath Balakrishnan
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Publication number: 20220318954Abstract: A method for removing reflections from images is disclosed. The method includes identifying one or more segments of an image, the one or more segments including a reflection; identifying one or more features of the one or more segments; removing the one or more features from the segments to generate one or more sanitized segments; and combining the one or more sanitized segments with the image to generate a sanitized image.Type: ApplicationFiled: March 31, 2021Publication date: October 6, 2022Applicants: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Vickie Youmin Wu, Wilson Hung Yu, Hakki Can Karaimer
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Patent number: 11461137Abstract: A first processing unit such as a graphics processing unit (GPU) pipelines that execute commands and a scheduler to schedule one or more first commands for execution by one or more of the pipelines. The one or more first commands are received from a user mode driver in a second processing unit such as a central processing unit (CPU). The scheduler schedules one or more second commands for execution in response to completing execution of the one or more first commands and without notifying the second processing unit. In some cases, the first processing unit includes a direct memory access (DMA) engine that writes blocks of information from the first processing unit to a memory. The one or more second commands program the DMA engine to write a block of information including results generated by executing the one or more first commands.Type: GrantFiled: December 19, 2019Date of Patent: October 4, 2022Assignee: Advanced Micro Devices, Inc.Inventor: Rex Eldon McCrary
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Patent number: 11462294Abstract: The low end operating voltage of an integrated circuit is adjusted. Oscillations are counted at a ring oscillator on the integrated circuit over a designated period of clock cycles. Based on the number of oscillations, a prediction model associated with a first set of device degradation data and a second set of static random-access memory (SRAM) low end operating voltage data is used to select a low end operating voltage limit for a processor on the integrated circuit. The low end operating voltage of the processor is set based on the selected low end operating voltage limit. These steps are repeated multiple times during operation of the processor. A method of testing integrated circuits to provide the data employed to produce the prediction model is also provided.Type: GrantFiled: December 14, 2020Date of Patent: October 4, 2022Assignee: Advanced Micro Devices, Inc.Inventors: Ashish Jain, Sriram Sundaram, Samuel Naffziger
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Patent number: 11461045Abstract: A processing unit is configured to access a first memory that supports atomic operations and a second memory via an interface. The second memory or the interface does not support atomicity of the atomic operations. A trap handler is configured to trap atomic operations and enforce atomicity of the trapped atomic operations. The processing unit selectively provides atomic operations to the trap handler in response to detecting that memory access requests in the atomic operations are directed to the second memory via the interface. In some cases, the processing unit detects a frequency of traps that result from atomic operations that include memory access requests to a page stored in the second memory. The processing unit transfers the page from the second memory to the first memory in response to the trap frequency exceeding a threshold.Type: GrantFiled: March 29, 2019Date of Patent: October 4, 2022Assignee: Advanced Micro Devices, Inc.Inventor: Mark Fowler
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Patent number: 11463084Abstract: A level shifting output circuit converts a signal from a core voltage to an I/O voltage without causing voltage overstress on transistor terminals in the level shifting output circuit. The output circuit includes protection transistors to protect various transistors in the output circuit from overvoltage conditions including those transistors coupled to I/O power supply nodes.Type: GrantFiled: September 1, 2021Date of Patent: October 4, 2022Assignee: Advanced Micro Devices, Inc.Inventors: Thanapandi Ganesan, Prateek Mishra, Jagadeesh Anathahalli Singrigowda, Dhruvin Devangbhai Shah, Animesh Jain, Girish Anathahalli Singrigowda
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Patent number: 11460879Abstract: Methods and apparatuses control electrical current supplied to a plurality of processing units in a multi-processor system. A plurality of current usage information corresponding to the processing units are received by a controller to determine a threshold current for each of the processing units. The controller determines a frequency reduction action and an instructions-per-cycle (IPC) reduction action for the each of the processing units based on the threshold current and regulates operations of the processing units based on the determined frequency and IPC reduction actions.Type: GrantFiled: June 25, 2021Date of Patent: October 4, 2022Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Amitabh Mehra, Richard Martin Born, Sriram Srinivasan, Sneha Komatireddy, Michael L. Golden, Xiuting Kaleen C. Man, Gokul Subramani Ramalingam Lakshmi Devi, Xiaojie He
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Publication number: 20220309126Abstract: A processing device is provided which comprises memory configured to store data and a processor configured to receive a portion of data of a first matrix comprising a first plurality of elements and receive a portion of data of a second matrix comprising a second plurality of elements. The processor is also configured to determine values for a third matrix by dropping a number of products from products of pairs of elements of the first and second matrices based on approximating the products of the pairs of elements as a sum of the exponents of the pairs of elements and performing matrix multiplication on remaining products of the pairs of elements of the first and second matrices.Type: ApplicationFiled: March 26, 2021Publication date: September 29, 2022Applicant: Advanced Micro Devices, Inc.Inventors: Pramod Vasant Argade, Swapnil P. Sakharshete, Maxim V. Kazakov, Alexander M. Potapov
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Publication number: 20220309125Abstract: A processing device is provided which comprises memory configured to store data and a processor. The processor comprises a plurality of MACs configured to perform matrix multiplication of elements of a first matrix and elements of a second matrix. The processor also comprises a plurality of logic devices configured to sum values of bits of product exponents values of the elements of the first matrix and second matrix and determine keep bit values for product exponents values to be kept for matrix multiplication. The processor also comprises a plurality of multiplexor arrays each configured to receive bits of the elements of the first matrix and the second matrix and the keep bit values and provide data for selecting which elements of the first matrix and the second matrix values are provided to the MACs for matrix multiplication.Type: ApplicationFiled: March 26, 2021Publication date: September 29, 2022Applicant: Advanced Micro Devices, Inc.Inventors: Swapnil P. Sakharshete, Pramod Vasant Argade, Maxim V. Kazakov, Alexander M. Potapov
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Publication number: 20220309729Abstract: A method of tiled rendering is provided which comprises dividing a frame to be rendered, into a plurality of tiles, receiving commands to execute a plurality of subpasses of the tiles and interleaving execution of same subpasses of multiple tiles of the frame. Interleaving execution of same subpasses of multiple tiles comprises executing a previously ordered first subpass of a second tile between execution of the previously ordered first subpass of a first tile and execution of a subsequently ordered second subpass of the first tile. The interleaving is performed, for example, by executing the plurality of subpasses in an order different from the order in which the commands to execute the plurality of subpasses are stored and issued. Alternatively, interleaving is performed by executing one or more subpasses as skip operations such that the plurality of subpasses are executed in the same order.Type: ApplicationFiled: December 29, 2021Publication date: September 29, 2022Applicant: Advanced Micro Devices, Inc.Inventors: Ruijin Wu, Mika Tuomi, Paavo Sampo Ilmari Pessi, Anirudh R. Acharya
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Publication number: 20220309606Abstract: Techniques for managing register allocation are provided. The techniques include detecting a first request to allocate first registers for a first wavefront; first determining, based on allocation information, that allocating the first registers to the first wavefront would result in a condition in which a deadlock is possible; in response to the first determining, refraining from allocating the first registers to the first wavefront; detecting a second request to allocate second registers for a second wavefront; second determining, based on the allocation information, that allocating the second registers to the second wavefront would result in a condition in which deadlock is not possible; and in response to the second determining, allocating the second registers to the second wavefront.Type: ApplicationFiled: March 26, 2021Publication date: September 29, 2022Applicant: Advanced Micro Devices, Inc.Inventors: Pramod Vasant Argade, Martin G. Sarov, Milind N. Nemlekar
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Patent number: 11455766Abstract: A processor selectively adjusts the precision of data for different functional units. Specified functional units of the processor, such as shader processing unit of a graphics processing unit (GPU) include a zeroing module to store, based on the states of corresponding precision flags, a data value of zero at specified portion of an input and/or output data operand. The functional unit then processes the data including the zeroed portion. Because a portion of the data has been zeroed, the functional unit consumes less power during data processing. Furthermore, the precision flags are set such that the reduced precision of the data does not significantly impact a user experience.Type: GrantFiled: September 18, 2018Date of Patent: September 27, 2022Assignee: Advanced Micro Devices, Inc.Inventors: Pramod V. Argade, Daniel Nikolai Peroni
