Abstract: The present invention provides a method for forming a low-k dielectric structure on a substrate 10 that includes depositing, upon the substrate, a dielectric layer 12. A multi-film cap layer 18 is deposited upon the dielectric layer. The multi-film cap layer includes first 181 and second 182 films, with the second film being disposed between the dielectric layer and the first film. The first film typically has a removal rate associated therewith that is less than the removal rate associated with the second film. A deposition layer 20 is deposited upon the multi-film cap layer and subsequently removed. The properties of the multi-film cap layer are selected so as to prevent the dielectric layer from being exposed/removed during removal of the deposition film. In this manner, a deposition layer, having variable rates of removal, such as copper, may be planarized without damaging the underlying dielectric layer.

Abstract: A method and system for deferring transmission of a data packet over a home network is disclosed, where the home network includes a host media access controller program and a media access controller. The method and system include transmitting a first transmit signal from the host media access controller program to the media access controller (MAC) to transmit a data packet, and asserting a transmit start signal from the MAC in response. The method and system further include receiving a carrier sense signal on the MAC indicating activity on a transmission medium, and delaying assertion of a final transmit signal when it is determined that both the transmit start signal and the carrier sense signal are active, thereby avoiding packet collisions.

Abstract: A method comprised of forming a process layer above a wafer, forming an ARC layer above the process layer, determining at least one optical characteristic of the ARC layer, and determining, based upon the determined optical characteristic of the ARC layer, at least one parameter of a stepper exposure process. The present invention is also directed to a system that may be used to perform the methods described herein. In one embodiment, the system is comprised of an optical metrology tool for measuring at least one optical characteristic of an ARC layer formed above a process layer, a controller for determining, based upon data obtained from the optical metrology tool, at least one parameter of a stepper exposure process, and a stepper tool for performing the exposure process comprised of the determined at least one parameter.

Abstract: A cache memory comprising: 1) a tag array comprising a plurality of tag entry locations that are accessed by R of the M least significant bits of an N-bit received address and stored an address tag comprising the (N-M) most significant bits of the N-bit received address. The cache memory also comprises 2) cache hit comparison circuitry for comparing the (N-M) most significant bits of an N-bit received address with an address tag and generating a HIT signal if a match occurs, and 3) tag array test circuitry for testing the operation of the tag array and the cache hit comparison circuitry.

Abstract: A method for dispatching based on metrology tool performance includes determining a precision metric associated with each of a plurality of metrology tools. A metrology request including context information is generated. A precision requirement for the metrology request is identified based on the context information. A set of the metrology tools capable of satisfying the metrology request is identified based on the precision requirement and the precision metrics. A manufacturing system includes a manufacturing execution system server and a metrology monitor. The manufacturing execution system server is configured to generate a metrology request including context information.

Abstract: A method of erasing a flash electrically erasable read only memory (EEPROM) device composed of a plurality of memory cells includes pre-programming the plurality of memory cells, applying an erase pulse to the plurality of memory cells followed by an erase verification. The erase verification is followed by soft programming any memory cells having a threshold voltage below a predetermined minimum level and applying a positive gate stress to the plurality of memory cells. The erase method prevents overerasing and provides a tightened threshold voltage distribution.

Abstract: A microprocessor employing a fixed position dispatch unit. The microprocessor includes a plurality of execution units each corresponding to an issue position and configured to execute a common subset of instructions. At least a first one of the execution units includes extended logic for executing a designated instruction that others of the execution units may be incapable of executing. The microprocessor also includes a plurality of decoders coupled to the plurality of execution units. The plurality of decoders may provide positional information to cause the designated instruction to be routed to the first execution unit. Further, the microprocessor includes a dispatch control unit configured to dispatch during a dispatch cycle, the designated instruction for execution by the first execution unit based upon the positional information. The dispatch control unit may further dispatch one or more instructions within the common subset of instructions during the same dispatch cycle.

Abstract: The present invention introduces circuitry and systems for performing two-dimensional motion compensation using a three-dimensional pipeline, as well as methods of operating the same. According to an exemplary embodiment, image processing circuitry is provided and includes both a two-dimensional image pipeline, which is operable to process two dimensional image data to generate successive two-dimensional image frames, and a three-dimensional image pipeline, which is operable to process three-dimensional image data to render successive three-dimensional image frames. The image processing circuitry further includes dual mode sub-processing circuitry, which is associated with each of the two- and three-dimensional image pipelines. The dual mode sub-processing circuitry is operable to perform motion compensation operations associated with the two-dimensional image pipeline in one mode and to perform rasterization operations associated the three-dimensional image pipeline in another mode.

Abstract: Nickel silicide formation with significantly reduced interface roughness is achieved by forming a diffusion modulating layer between the underlying silicon and nickel silicide layers. Embodiments include ion implanting nitrogen into the substrate and gate electrode, depositing a thin layer of titanium or tantalum, depositing a layer of nickel, and then heating to form a diffusion modulating layer containing nitrogen at the interface between the underlying silicon and nickel silicide layers.

Abstract: A random number generator and method thereto using an entropy register. The method includes providing a first plurality of bit entries in an entropy register and transmitting a bit value from each of a plurality of registers to one of the first plurality of bit entries in the entropy register. The random number generator comprises an entropy register configured to receive bits over a plurality of data lines that each couple to an individual entry in the entropy register. The random number generator may further include an entropy control unit configured to provide a value from the entropy register in response to a request for a random number.

Abstract: A method and apparatus for scheduling in an automated manufacturing environment, comprising are disclosed. The method includes detecting an occurrence of a predetermined event in a process flow; notifying a software scheduling agent of the occurrence; and reactively scheduling an action from the software scheduling agent responsive to the detection of the predetermined event. The apparatus is automated manufacturing environment including a process flow and a computing system. The computing system further includes a plurality of software scheduling agents residing thereon, the software scheduling agents being capable of reactively scheduling appointments for activities in the process flow responsive to a plurality of predetermined events.

Abstract: A method and apparatus for reducing latency in a peripheral interface circuit of an I/O node of a computer system. The apparatus includes a buffer coupled to a control unit. The buffer may be configured to receive data on a first bus and the control unit may be configured to generate a first command type in response to receiving a first quantity of data having invalid bytes within the buffer. The control unit may be further configured to generate a second command type in response to a receiving within the buffer a second quantity of data having no invalid bytes. Further, in response to receiving a particular transaction type, the control unit may be configured to generate the second command type before the first quantity of data is received within the buffer.

Abstract: A method of manufacturing a semiconductor device may include forming a fin on an insulator and forming a gate oxide on sides of the fin. The method may also include forming a gate structure over the fin and the gate oxide and forming a dielectric layer adjacent the gate structure. Material in the gate structure may be removed to define a gate recess. A width of a portion of the fin below the gate recess may be reduced, and a metal gate may be formed in the gate recess.

Abstract: A method is provided for configuring a final data set to use for modeling a manufacturing process, the method including requesting a real-time data set from a real-time database, requesting an historical data set from an historical database, and defining a required format for the final data set. The method also includes combining the real-time data set from the real-time database with the historical data set from the historical database using the required format for the final data set.

Abstract: A device for modulating a carrier signal simultaneously performs frequency translation, upsampling, and pulse shaping. The device includes a mapper generating a first data signal. A complex mixer and an upsampling device are used to increase the data value frequency and spectrum shift the data signal. A finite impulse response filter operating on the data signal generates a digital signal representing the modulated carrier.

Abstract: Various circuit devices, including diodes, and methods manufacturing therefor are provided. In one aspect, a method manufacturing is provided that includes forming a gate structure on a semiconductor portion of a substrate. The semiconductor portion has a first conductivity type. First and spacer structures are formed on opposite sides of the gate structure. A first impurity region of a second conductivity type is formed proximate the first spacer structure while the semiconductor portion lateral to the second spacer structure is masked. The first impurity region and the semiconductor portion define a junction. A width of the second spacer structure is reduced while the second spacer structure and the first impurity region are masked. A second impurity region of the first conductivity type is formed in the semiconductor portion proximate the second spacer structure. The method provides a diode with reduced series resistance.

Abstract: A processor is configured to support a programmable flags masking during processing of a system call instruction such as Syscall. The processor includes a register storing a mask, where an indication within the mask corresponds to each of a plurality of flags used by the processor. Based on the state of the indication, the processor may clear a corresponding flag or may retain the value of the corresponding flag. By programming the register appropriately, the desired clearing and retaining of the plurality of flags may be performed as part of the system call instruction. Flexibility may be provided for different operating systems having different sets of flags to be preserved or cleared.

Abstract: A memory cell with reduced short channel effects is described. A source region and a drain region are formed in a semiconductor substrate. A trench region is formed between the source region and the drain region. A recessed channel region is formed below the trench region, the source region and the drain region. A gate dielectric layer is formed in the trench region of the semiconductor substrate above the recessed channel region and between the source region and the drain region. A control gate layer is formed on the semiconductor substrate above the recessed channel region, wherein the control gate layer is separated from the recessed channel region by the gate dielectric layer.

Abstract: The invention provides a technique of monitoring the void formation in a damascene interconnection process. According to the invention, a test structure is provided that includes at least two damascene structures that have at least one different cross-sectional geometric parameter. To monitor the void formation, the test structure is cut to expose a cross-sectional view to the damascene structures. The cross-sectional view is then inspected and the void formation is investigated in each of the damascene structures. The invention is particularly applicable to multi-level copper-based dual-damascene interconnection processes to monitor the voiding at the interface between barrier layers and bottom metal trenches. The invention allows monitoring of the void formation by locating only one structure on the chip and performing only one cut.

Abstract: Accurate determination of gate dielectric thickness is required to produce high-reliability and high-performance ultra-thin gate dielectric semiconductor devices. Large area gate dielectric capacitors with ultra-thin gate dielectric layers suffer from high gate leakage, which prevents the accurate measurement of gate dielectric thickness. Accurate measurement of gate dielectric thickness of smaller area gate dielectric capacitors is hindered by the relatively large parasitic capacitance of the smaller area capacitors. The formation of first and second dummy structures on a wafer allow the accurate determination of gate dielectric thickness. First and second dummy structures are formed that are substantially similar to the gate dielectric capacitors except that the first dummy structures are formed without the second electrode of the capacitor and the second dummy structures are formed without the first electrode of the capacitor structure.