Abstract: There is disclosed a personal access device (PAD) capable of browsing web sites on an Internet protocol (IP) network and also capable of operating as a cordless phone that provides a conventional phone connection or a voice-over-IP phone connection. The personal access device comprises: 1) a radio frequency (RF) transceiver for wirelessly communicating with a base station coupled to the IP network, wherein the RF transceiver transmits IP data packets to the base station and receives IP data packets from the base station; and 2) a PAD controller for executing an Internet browser application and displaying web pages associated with the web sites on a display screen of the personal access device. The PAD controller is also capable of transmitting voice data to, and receiving voice data from, the base station via the RF transceiver.

Abstract: A metal layer is formed by means of an electroless plating process, wherein a surface region of an underlying material is catalytically activated in that a catalyst is deposited or incorporated by CVD, PVD or ALD during and/or after the deposition of the underlying material. In this way, superior metal seed layers may be formed even in high aspect ratio vias of metallization structures.

Abstract: A method and system for operating a bus according to a plurality of bus protocols, including a legacy bus protocol. A first signal is transmitted indicating a transaction request of a first kind. A second signal is transmitted indicating a transaction request of a second kind. The second signal may be decoded according to a plurality of protocols. The first signal is decoded prior to decoding the second signal. The decode of the first signal indicates which of the plurality of protocols should be used to decode the second signal. A computer system includes a bus, preferably an LPC bus, coupling two or more devices.

Abstract: A method and apparatus for reordering transactions in a packet-based fabric using I/O Streams. Packet bus transactions may flow upstream from node to node on a non-coherent I/O packet bus. Some peripheral buses place ordering constraints on their bus transactions to prevent deadlock situations. When a packet transaction originating on a peripheral bus with ordering constraints is translated to a packet bus such as the non-coherent I/O packet bus, those same ordering constraints may be mapped over to the packet bus transactions. To efficiently handle the packets and prevent deadlock situations, packets may be handled and reordered on an I/O stream basis. Thus, reordering logic may consider I/O streams independently and therefore only reorder transactions within an I/O stream and not across more than one I/O stream.

Abstract: A microprocessor may include several execution units and a scheduler coupled to issue operations to at least one of the execution units. The scheduler may include several entries. A first entry may be allocated to a first operation. The first entry includes a source status indication for each of the first operation's operands. Each source status indication indicates whether a value of a respective one of the first operation's operands is speculative. The scheduler is configured to update one of the first entry's source status indications to indicate that a value of a respective one of the first operation's operands is non-speculative in response to receiving an indication that a value of a result of a second operation is non-speculative.

Abstract: A method for providing a low power memory array is provided. The method includes partitioning a memory array into at least two memory sections. Each memory section comprises a plurality of memory cells. A sense amplifier is provided for the memory sections. An operation request for a specified memory cell in one of the memory sections is received. The memory section comprising the specified memory cell is accessed. The requested operation is performed on the specified memory cell.

Abstract: A network switch, configured for performing layer 2 and layer 3 switching in an Ethernet (IEEE 802.3) network without blocking of incoming data packets, includes network switch ports, each including a flow module configured for generating a packet signature based on layer 3 information within a received data packet. The flow module generates first and second hash keys according to a prescribed hashing function upon obtaining first and second portions of layer 3 information. The flow module combines the first and second hash keys to form the packet signature, and searches an on-chip signature table that indexes addresses of layer 3 switching entries by entry signatures, where the entry signatures are generated using the same prescribed hashing function on the first and second layer 3 portions of the layer 3 switching entries.

Abstract: A dependency instruction encodes dependency information among a group of instructions. A processor decodes the dependency instruction associated with the group of instructions. The processor can then execute the group of instructions in an order based on the dependency information in the dependency instruction. The dependency information may be encoded in a neutral instruction so processors that do not support dependency instructions can execute a program containing them.

Abstract: A computer system employs virtual channels and allocates different resources to the virtual channels. More particularly, the computer system provides a posted commands virtual channel separate from the non-posted commands virtual channel for routing posted and non-posted commands or requests through coherent and noncoherent fabrics within the computer system. Because separate resources are allocated to the virtual channels in the computer system, posted requests may be allowed to become unordered with other requests from the same source. Implementation of a separate posted commands virtual channel may allow the computer system to maintain compatibility with I/O systems in which posted write requests may become unordered with previous posted requests (e.g., the Peripheral Component Interconnect Bus, or PCI). Implementation of the separate posted commands virtual channel thus may assist in providing deadlock-free operation.

Abstract: A method and system for reading flash memory. A leakage current of a common bit line comprising the flash memory cell is accessed. A read current of the flash memory cell is accessed. The leakage current is eliminated from the read current to determine a cell current. The cell current is compared to an erase verify cell current. The currents may be directly subtracted, or they may be converted to corresponding voltages and the voltages subtracted. Advantageously, cells may be correctly verified for erasure without a preliminary search and recovery of over erased bits. As a beneficial result, the search and recovery of over erased bits does not need to be performed during an erase process. Advantageously, such steps may be eliminated from an erase process, recovering the time otherwise required to perform such steps, and thereby speeding up the erase process.

Abstract: Semiconductor devices with improved transistor performance are fabricated by forming a composite oxide/nitride liner under a gate electrode sidewall spacer. Embodiments include depositing a conformal oxide layer by decoupled plasma deposition, depositing a conformal nitride layer by decoupled plasma deposition, depositing a spacer layer and then etching.

Abstract: When changing a dopant species in an implantation tool, typically a clean process is performed to reduce cross-contamination, which is considered a major issue in implant cycles applied in advanced CMOS processes. Especially, the employment of an implanter previously used for heavy ions may generate increased cross-contamination when subsequently used for boron or phosphorus implants at moderate energies. A clean implant process using xenon gas may effectively reduce this cross-contamination at shorter process times compared to a conventional argon clean step.

Abstract: Disclosed are a method of and a system for monitoring extreme ultraviolet (EUV) lithography mask flatness. An EUV mask, which is chucked to a chuck, can be scanned with a capacitance probe that generates elevation data for the EUV mask. From the elevation data, a first flatness profile can be generated. In one embodiment, the EUV mask can be rotated and rescanned.

Abstract: Leakage, capacitance and reliability degradation of interconnects fabricated in low-k dielectric materials, particularly porous low-k dielectric material, due to penetration by a barrier metal and/or barrier metal precursor during damascene processing is prevented by depositing a conformal, heat stable dielectric sealant layer on sidewalls of the low-k dielectric material defining the damascene opening. Embodiments include forming a dual damascene opening in a porous, low-k organosilicate layer, the organosilicate having a pendant silanol functional group, depositing a siloxane polymer having a silylating functional group which bonds with the pendant silanol group to form the sealant layer, depositing a Ta and/or TaN barrier metal layer by CVD or ALD and filling the opening with Cu or a Cu alloy.

Abstract: A method and an apparatus for affecting dispatch and/or disposition of a workpiece. A process step upon a workpiece is performed based upon a predetermined routing plan. An end-of-line parameter is modeled based upon the process performed upon the workpiece. A workpiece routing/disposition process is performed based upon modeling an end-of-line (EOL) parameter. The workpiece routing/disposition process includes using a controller to modify the routing plan.

Abstract: A network device that controls the communication of data frames between stations includes a number of receive ports that receive data frames from the stations and a number of output ports that transmit the data frames to their intended destinations. The network device also includes a number of output queues that store data forwarding information associated with the received data frames. The network device partitions each of the output queues into a number of portions corresponding to the priorities supported by the network device. The number of portions and the size of each portion of the output queues may be programmable by the user.

Abstract: A system selects a tone at which a pilot sequence is to be transmitted. The system includes logic configured to adaptively select a tone on which the pilot sequence is transmitted based one or more conditions in the transmission system.

Abstract: Methods of using dynamic metrology sampling techniques for identified lots, and a system for performing such methods are disclosed. In one illustrative embodiment, the method comprises identifying at least one wafer to be processed, identifying a process tool in which at least one wafer is to be processed, obtaining enhanced metrology data regarding a process operation to be performed in the identified process tool prior to processing the identified at least one wafer in the identified process tool, and positioning at least one wafer in the identified process tool and performing the process operation thereon.

Abstract: A networking interface device for coupling a system host having one of a plurality configurations to a network medium. The device having a peripheral component interconnect (PCI) interface for coupling the interface device to a system host configured with a PCI based system bus interface; a medium independent interface (MII) for coupling the interface device to a system host configured with a media access controller (MAC) based system bus interface; and a control block for determining whether the interface device is operably coupled to a system host having a PCI based system bus interface or a MAC based system bus interface.

Abstract: A method for detecting sequential processing effects on integrated circuits to be manufactured in a manufacturing process, includes: determining a first random sequence for a plurality of wafers; performing a first process step on the plurality of wafers by a first process tool in accordance with the first random sequence; determining a second random sequence for the plurality of wafers; and performing a second process step on the plurality of wafers by a second process tool in accordance with the second random sequence. The method performs randomization of wafer processing sequences at the process tool itself. By performing randomization of wafer processing sequences at the process tool, the need for separate wafer handlers is eliminated, resulting in significant cost reduction, clean-room space savings, improved yield, improved manufacturing cycle time, and improved signal-detection capabilities.