Abstract: The present invention facilitates semiconductor devices by aiding the efficiency in the way individual devices change states in a semiconductor array. State change voltages can be applied to a single device in the array of semiconductor devices without the need for transistor-type voltage controls. The diodic effect of the present invention facilitates this activity by allowing specific voltage levels necessary for state changes to only occur at the desired device. In this manner, an array of devices can be programmed with varying data or states without utilizing transistor technology. The present invention also allows for an extremely efficient method of producing these types of devices, eliminating the need to manufacture costly external voltage controlling semiconductor devices.

Abstract: An integrated enterprise resource planning and manufacturing system which includes a middleware component, a fabrication facility coupled to the middleware component, a real time dispatcher application program interface coupled between the fabrication facility and the middleware component, a work in progress application program interface coupled between the fabrication facility and the middleware component, and an enterprise resource planning system coupled to the middleware component. The fabrication facility includes a manufacturing execution system and a real time dispatch system. The manufacturing execution system tracks overall processing of semiconductor wafers. The real time dispatch system provides near real time information regarding processing of semiconductor wafers. The real time dispatcher application program interfaces publishing information to the middleware component.

Abstract: A decode unit is coupled to receive instruction bytes and to dispatch instructions to an execution subsystem. The decode unit comprises circuitry divided into a pipeline including a plurality of pipeline stages, wherein the circuitry is configured to concurrently initiate decode of a plurality of instructions and to dispatch at least an initial instruction of the plurality of instructions from a first pipeline stage of the plurality of pipeline stages. Furthermore, the circuitry is configured to dispatch at least one remaining instruction of the plurality of instructions from a second pipeline stage of the plurality of pipeline stages. The second pipeline stage is subsequent to the first pipeline stage in the pipeline.

Abstract: A novel method of reading descriptors by a network interface is provided in a computer system having a host CPU and a memory containing descriptors arranged in a list. The method includes reading at least two descriptors in a single PCI bus transaction. The network interface comprises a PCI interface for providing connection to the system via a PCI bus, and descriptor management logic for reading descriptors from the memory via the PCI interface. The descriptor management logic is configured for reading more than one descriptor in a single PCI read transaction. After reading a first descriptor, the descriptor management logic reads a second descriptor following the first descriptor regardless of whether the second descriptor is owned by the network interface or the host CPU. The network interface performs a read operation to read a message buffer associated with the second descriptor if this descriptor is owned by the network interface.

Abstract: A programmable interconnect structure and method of operating the same provides a programmable interconnection between electrical contacts. The interconnect includes material that has a reversibly programmable resistance. The material includes a molecular matrix with ionic complexes distributed through the molecular matrix. Application of an electrical field or electric current causes the molecular composite material to assume a desired resistivity (or conductivity) state. This state is retained by the molecular composite material to thus form a conductive or a non-conductive path between the electrical contacts.

Abstract: A computer system that has multiple performance states periodically obtains utilization information for a plurality of tasks operating on the processor and determines processor utilization according to the utilization information for the plurality of tasks. The system compares the processor utilization to at least one threshold and selectively adjusts a current processor performance state to another performance state according to the comparison.

Abstract: A system for analyzing diagnostic information associated with a spin track is provided. The system includes one or more analysis systems that collect diagnostic information from one or more spin tracks. The system further includes one or more maintenance systems that schedule routine and/or special maintenance based on analysis of the diagnostic information. An alternative aspect of the system further includes one or more control information systems that generate of feedback control information employed in adapting the processes performed by the spin track.

Abstract: A system may include a scheduler and an execution core. The scheduler includes an entry allocated to an operation. The entry includes a non-speculative tag and a speculative tag, and both the non-speculative tag and the speculative tag are associated with a first operand of the operation. The scheduler is configured to issue the operation in response to a data value identified by the speculative tag being available. The execution core may be configured to execute the operation using the data value identified by the speculative tag. The scheduler may be configured to reissue the operation if the non-speculative tag appears on a result bus.

Abstract: In a high power input/output SOI semiconductor structure, the transistors thereof are laid out in a manner so that the high current density transistors, subject to the greatest heat buildup, are spaced apart in a manner as to avoid significant heat buildup.

Abstract: An interface for a semiconductor fabrication facility which includes a real time dispatch system providing near real time information regarding processing of semiconductor wafers and a middleware component. The interface includes a work in progress application program interface coupled between the fabrication facility and the middleware component. The work in progress application program interface provides a common interface for communicating between the fabrication facility and the middleware component.

Abstract: The operability of light-based semiconductor die analysis is enhanced using a method and arrangement that directs light between a light source and a die. In one example embodiment of the present invention, a light source is directed to a die in a semiconductor analysis arrangement using a fiber optic cable. The analysis arrangement is adapted to use light received via the fiber optic cable to analyze the die. The analysis includes one or more light-based applications, such as stimulating a selected portion of the die with the light and detecting a response therefrom. In this manner, light can be directed to a die in a variety of analysis implementations, such as for analyzing a die in a test chamber.

Abstract: A microprocessor may include a dispatch unit configured to dispatch load and store operations and a load store unit configured to store information associated with load and store operations dispatched by the dispatch unit. The load store unit includes a STLF (Store-to-Load Forwarding) buffer that includes a plurality of entries. The load store unit is configured to generate an index dependent on at least a portion of an address of a load operation, to use the index to select one of the plurality of entries, and to forward data included in the one of the plurality of entries as a result of the load operation.

Abstract: A process tool for electrochemically treating a substrate is configured to reduce the oxygen concentration and/or the sulfur dioxide concentration in the vicinity of the substrate so that corrosion of copper may be reduced. In one embodiment, a substantially inert atmosphere is established within the process tool including a plating reactor by providing a continuous inert gas flow and/or by providing a cover that reduces a gas exchange with the ambient atmosphere. The substantially inert gas atmosphere may also be maintained during further process steps involved in electrochemically treating the substrate including required transportation steps between the individual process steps.

Abstract: A method and an apparatus for performing process control at an interconnect level. A process step upon a workpiece is performed. Manufacturing data relating to an interconnect location on the workpiece is acquired. An interconnect characteristic control process is performed based upon the manufacturing data. The interconnect characteristic control process includes controlling a process relating to a structure associated with the interconnect location on the workpiece to control a characteristic relating to the interconnect location.

Abstract: A method and an apparatus for preventing misalignment of semiconductor packaging assembly materials. In particular, a method of fabricating a fully aligned flip-chip assembly having a variable pitch packaging substrate, involves: providing a set of input data; calculating a set of intermediate data using the input data set; calculating a set of final substrate pad coordinates using the intermediate data set, thereby providing a set of output data; providing a packaging substrate having a plurality of substrate pads thereon formed according to the output data set to compensate for any inchoate thermogeometric hysteresis arising from any mismatched coefficients of thermal expansion, and thereby fabricating the flip-chip assembly having a variable pitch packaging substrate, and an assembly thereby fabricated which is more robust to any temperature-induced stress.

Abstract: The adhesion properties of a metal interconnect structure are enhanced by selectively depositing a barrier layer component having good adhesion to an underlying metal on the bottom surface of a via. Then, a further barrier layer having superior adhesion characteristics for the dielectric is formed on the dielectric sidewalls of the via, so that excellent adhesion to the dielectric and the underlying metal is achieved. The selectivity of the deposition may be accomplished by exploiting the capabilities of modem IPVD tools.

Abstract: Accurate determination of gate dielectric thickness is required to produce high-reliability and high-performance ultra-thin gate dielectric semiconductor devices. Large area gate dielectric capacitors with ultra-thin gate dielectric layers suffer from high gate leakage, which prevents the accurate measurement of gate dielectric thickness. Accurate measurement of gate dielectric thickness of smaller area gate dielectric capacitors is hindered by the relatively large parasitic capacitance of the smaller area capacitors. The formation of first and second dummy structures on a wafer allow the accurate determination of gate dielectric thickness. First and second dummy structures are formed that are substantially similar to the gate dielectric capacitors except that the first dummy structures are formed without the second electrode of the capacitor and the second dummy structures are formed without the first electrode of the capacitor structure.

Abstract: A system provides flow control in a network device. The system includes output queues that correspond to the output ports of the network device, a mask register, a first logic device, and a second logic device. Each of the output queues generates signals relating to the priority levels associated with the corresponding output port when at least a predetermined number of items are stored in the output queue. The mask register generates mask signals relating to the priority levels associated with a particular one of the output ports. The first logic device generates first flow control signals related to the priority levels associated with the particular output port based on the signals from the output queues and the mask signals associated with the priority levels and the particular output port. The second logic device generates a second flow control signal based on the first flow control signals from the first logic device.

Abstract: A communications system includes physical layer hardware and a processing unit. The physical layer hardware is adapted to communicate data over a communications channel in accordance with a plurality of control codes. The physical layer hardware is adapted to demodulate an incoming analog signal to generate a digital receive signal and modulate a digital transmit signal to generate an analog transmit signal. The processing unit is adapted to execute a privileged driver for interfacing with the physical layer hardware. The privileged driver includes program instructions for implementing a protocol layer to decode the digital receive signal, encode the digital transmit signal, and configure the physical layer hardware for receipt of the digital receive signal and transmission of the digital transmit signal based on the plurality of control codes.

Abstract: The present neutron sensing device includes a first substantially planar array of flash memory cells, a second substantially planar array of flash memory cells having an edge adjacent an edge of the first substantially planar array of flash memory cells, and a third substantially planar array of flash memory cells having a first edge adjacent an edge adjacent an edge of the first substantially planar array of flash memory cells and a second edge adjacent an edge of the second substantially planar array of flash memory cells.