Abstract: A system for monitoring and controlling a boron phosphorous doped silicon oxide (BPSG) deposition and reflow process is provided. The system includes one or more light sources, each light source directing light to one or more portions of a wafer upon which BPSG is deposited. Light reflected from the BPSG is collected by a measuring system, which processes the collected light. Light passing through the BPSG may similarly be collected by the measuring system, which processes the collected light. The collected light is indicative of the conformality of the BPSG deposition of the respective portions of the wafer. The measuring system provides BPSG deposition related data to a processor that determines the BPSG deposition of the respective portions of the wafer. The system also includes a plurality of reflow controlling devices, each such device corresponding to a respective portion of the wafer and providing for the heating and/or cooling thereof.

Abstract: A process for forming a transistor having a gate width of less than 70 nm is disclosed herein. The process includes E-beam irradiation a gate patterned on a photoresist layer, trimming the gate patterned on the photoresist layer, and etching the gate patterned on the photoresist layer to a polysilicon layer disposed below the photoresist layer.

Abstract: A low impedance electrical pathway from decoupling capacitance located on a circuit board to an integrated circuit chip. The integrated circuit includes multiple power and ground C4 bumps and is positioned on a first side of an integrated circuit carrier which is positioned on a first side of a circuit board. The integrated circuit carrier includes lateral conductors such as voltage and ground power planes. Power and ground carrier vias extend from the voltage and ground power planes, respectively, to the first side of the carrier, and power and ground subgroups of carrier vias extend from the voltage and ground power planes, respectively, to power and ground solder balls on a second side of the carrier. The circuit board includes power and ground plated through holes extending from contact pads on the first side of the circuit board to contact pads on a second side of the circuit board. Decoupling capacitors are positioned on the second side of the circuit board.

Abstract: A method for fabricating a body-tied SOI transistor with reduced body resistance is presented. During the wafer fabrication process, a semiconductor wafer is placed in an ion implantation device and oriented to a first position relative to a beam path of the ion implantation device in order to obtain a substantially non-orthogonal twist orientation between the beam path and the transistor gate edge. Following this orientation of the first position, an ion species is implanted into a first implantation region. The wafer is then rotated to a second substantially non-orthogonal twist orientation, where another ion implantation is conducted. This process continues in the same manner, such that further substantially non-orthogonal twists and ion implantations are conducted, until the desired number of implantation areas is created. Halo or pocket implants are an example of the type of implantations to which the technique may be applied.

Abstract: An outer edge ring of a semiconductor wafer is polished to prevent delamination and peeling-off of at least one layer of material deposited near the outer edge of the semiconductor wafer during fabrication of integrated circuits. The semiconductor wafer is mounted on a wafer chuck, and the wafer chuck holding the semiconductor wafer is rotated such that the semiconductor wafer rotates. A polishing pad is moved toward the semiconductor wafer as the semiconductor wafer is rotating. The polishing pad has a polishing surface that faces and contacts the outer edge ring of the semiconductor wafer as the polishing pad is moved toward the semiconductor wafer to polish the outer edge ring of the semiconductor wafer. The outer edge ring has the at least one layer of material that is polished off by the polishing surface of the polishing pad.

Abstract: For determining optimum optical proximity corrections (OPCs) for a mask pattern, mask areas are formed on a reticle with each mask area having the mask pattern of polygons that are modified with respective OPCs perturbations. A respective patterned area is fabricated on a semiconductor wafer from each mask area of the reticle. A respective microscopy image of each respective patterned area is generated to determine a respective error function for each mask area by comparing a desired image of the mask pattern and the respective microscopy image. The optimum OPCs are determined as the respective OPCs perturbations corresponding to one of the mask areas having the respective error function that is a minimum of the mask areas.

Abstract: Dopant deactivation, particularly at the Si/silicide interface, is avoided by forming deep source/drain implants after forming silicide layers on the substrate and activating the source/drain regions by laser thermal annealing. Embodiments include forming source/drain extensions, forming metal silicide layers on the substrate surface and gate electrode, forming preamorphized regions under the metal silicide layers in the substrate, ion implanting to form deep source/drain implants overlapping the preamorphized regions and extending deeper into the substrate then the preamorphized regions, and laser thermal annealing to activate the deep source/drain regions.

Abstract: A method of making organic memory cells made of two electrodes with a controllably conductive media between the two electrodes is disclosed. The controllably conductive media contains an organic semiconductor layer that contains a photosensitive compound. The organic semiconductor layer is formed into memory cells using patterning techniques.

Abstract: A method of forming a fuse for use in an integrated circuit using an amorphous carbon mask includes providing a mask material layer comprising amorphous carbon over a conductive layer. The mask material layer is doped with nitrogen, and an anti-reflective coating (ARC) feature is formed over the mask layer. A portion of the mask material layer is removed according to the ARC feature to form a mask, and the ARC feature is removed to form a warped mask. The conductive layer is patterned according to the warped mask, the warped mask is removed, and a silicide layer is provided over the patterned conductive layer.

Abstract: A method of generating a lifetime projection for semiconductor devices is disclosed. The disclosed method includes collecting lifetime information from a plurality of semiconductor devices at more than one stress condition. The method also includes determining the median lifetime for semiconductor devices at each of the stress conditions. Further, the method includes calculating a lifetime at each stress condition at which a predetermined percentage of the devices will exceed and extrapolating the lifetime for devices used at operating conditions.

Abstract: According to one exemplary embodiment, a memory array comprises first and second isolation regions situated in a substrate, where the first and second isolation regions are separated by a separation distance. The memory array further comprises a trench situated between the first and second isolation regions, where the trench defines trench sidewalls and a trench bottom in the substrate. The memory array further comprises a tunnel oxide layer situated between the first and second isolation regions, where the tunnel oxide layer is situated on the trench sidewalls and the trench bottom. According to this embodiment, the memory array further comprises a channel region situated underneath the tunnel oxide layer and extending along the trench sidewalls and the trench bottom, where the channel region has an effective channel width, where the effective channel width increases as a height of the trench sidewalls increases.

Abstract: A microprocessor includes a plurality of execution units each configured to execute instructions and an instruction dispatch circuit configured to dispatch instructions for execution by the plurality of execution units. A power management control unit includes a programmable unit for storing information specifying one or more reduced power modes. In the implementation of a first performance throttling technique, the power management control unit may be configured to cause the instruction dispatcher to limit the dispatch of instructions to a limited number of execution units. In the implementation of a second performance throttling technique, the power management control unit may be configured to limit the dispatch of instructions from the instruction dispatcher on every cycle, upon every other cycle, upon every third cycle, upon every fourth cycle, and so on.

Abstract: The present invention relates to an equipment interface which obtains data communicated between a tool, such as a semiconductor manufacturing tool, and its host computer system in real-time via a point-to-point connection. The equipment interface distributes the data automatically and continually to other remote application programs without the need for hardware to be added to the tool or to the host computer system.

Abstract: A method, system and computer program product to isolate information related to performing a manufacturing process, called a configuration document, from the context in which the information is used. A context/configuration association can be independently established between a process context and a context-free configuration document including instructions for performing a manufacturing process. Because the context/configuration association is independent of both the process context and the context-free configuration document, the context/configuration association can be independently reviewed and approved without affecting other process contexts or configuration documents.

Abstract: A method of semiconductor integrated circuit fabrication. Specifically, one embodiment of the present invention discloses a method for reducing shallow trench isolation (STI) corner recess of silicon in order to reduce STI edge thinning for peripheral thin gate transistor devices 480 in an integrated circuit 400 comprising flash memory devices 380, and both thick 390 and thin 480 gate transistor devices. The method begins by forming a tunnel oxide layer 310 over a semiconductor substrate 430 for the formation of the flash memory devices 380 (step 220). A mask 350 is formed over the thin gate transistor devices 480 to inhibit formation of a thick gate oxide layer 360 for the formation of the thick gate transistor devices 390 (step 230). The mask 350 reduces shallow trench isolation (STI) recess by eliminating removal of the thick gate oxide layer 360 before forming a thin oxide layer 410 for the thin gate transistor devices 480.

Abstract: A dual damascene air gap process reduces the dielectric constant, and extends CVD low-k technology by removing the sacrificial intra-metal dielectric between conductive lines by patterned etching and replacement with lower k material. The void space between the narrowly spaced conductive lines is sealed in by the non-conformal CVD deposition, thereby further reducing the overall capacitance of the dual damascene interconnect formation.

Abstract: Spacer etch trim techniques are provided. The method controllably trims a multi-film stack spacer utilizing a self-limiting etch technique. The method may use a dry etch etcher with low bias power. The dry etch process may also use other modified parameters, such as gas flows and various pressures.

Abstract: A method and an apparatus for selectively processing a layer of a workpiece based upon dependencies with other layers in the workpiece. A process step upon the workpiece is performed. Metrology data relating to the workpiece is acquired. A process adjustment relating to a first layer on the workpiece is calculated based upon the metrology data. A determination whether an error on a second layer on the workpiece would occur in response to an implementation of the process adjustment performed on the first layer. A magnitude of the calculated process adjustment is reduced in response to a determination that the second layer would be affected in response to the implementation of the process adjustment.

Abstract: A method of manufacturing a semiconductor device includes depositing a layer over a substrate and etching the layer to form a grating structure, a cross bridge test structure and a line width measurement structure. The grating structure includes a plurality of parallel lines and one of the multiple parallel lines is connected to the line width measurement structure and the cross bridge test structure. A scatterometry test is performed on the grating structure to obtain a line width and this width is compared to a line width calculated using the line width measurement structure. A semiconductor device is also disclosed.

Abstract: The invention, in a first aspect, is a method for mitigating edge effects in a decompressed video image. The method comprises first reads an N×N group of pixels defining a vertical edge between two blocks in a video frame row by row into N registers, wherein N is a predetermined number defining the length of a filter. The content of the N registers is then transposed and then filtered in the filter. The filtered content of the N registers is then transposed and stored back from where it was read. In other aspects, the invention is a program storage device encoded with instructions that, when executed by a computer, perform such a method; a computer programmed to perform such a method; and a computing system capable of performing such a method.