Patents Assigned to Advanced Micro Devices, Incs.
  • Publication number: 20250209000
    Abstract: In accordance with the described techniques, a device includes a memory system and a processor communicatively coupled to the memory system. The processor receives a load instruction from the memory system instructing the processor to load data associated with an address. In response, the processor performs a lookup for the address in a bloom filter that tracks zero value cache lines that have previously been accessed. Based on the lookup indicating that a hash of the address is present in the bloom filter, the processor generates zero value data. Furthermore, the processor processes one or more dependent instructions using the zero value data.
    Type: Application
    Filed: December 21, 2023
    Publication date: June 26, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Varun Agrawal, Georgios Tziantzioulis
  • Publication number: 20250208640
    Abstract: The disclosed voltage regulator circuit includes an NMOS as the main power device that is coupled to a regulated voltage output. A sensing circuit senses the regulated voltage output, and a reference voltage circuit supplies a correct bias to the flipped-source follower, which amplifies the sensed voltage output. A voltage inversion circuit such as a current mirror provides an inverting gain stage for the sensed voltage output, for driving the NMOS. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: March 29, 2023
    Publication date: June 26, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Luca Ravezzi
  • Publication number: 20250210453
    Abstract: A thermal management system for an integrated circuit can include plural micro vapor chambers each configured to operate within their local environment. An exemplary system includes a semiconductor die, a first micro vapor chamber coupled with a first region of the semiconductor die, and a second micro vapor chamber coupled with a second region of the semiconductor die.
    Type: Application
    Filed: December 22, 2023
    Publication date: June 26, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Joshua Taylor Knight, William R. Alverson, Amitabh Mehra, Grant Evan Ley, Anil Harwani, Jerry A. Ahrens
  • Publication number: 20250210591
    Abstract: An integrated circuit die includes a set of electronic circuits disposed on a semiconductor material. The integrated circuit die also includes one or more through-silicon vias that vertically span the semiconductor material to transmit data signals. Additionally, the integrated circuit die includes a programmable delay element integrated with the set of electronic circuits on the semiconductor material and configured to delay data signals. Various other apparatuses, systems, and methods are also disclosed.
    Type: Application
    Filed: December 22, 2023
    Publication date: June 26, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Russell Schreiber, Stephen Dussinger, Eric Busta, Ryan J. Miller, John Wuu
  • Publication number: 20250208869
    Abstract: A disclosed method for consolidating eligible vector instructions can include detecting a plurality of vector instructions within a queue of an integrated circuit. The method can also include consolidating the plurality of vector instructions into a single vector instruction based at least in part on the plurality of instructions satisfying one or more criteria. The method can further include forwarding the single vector instruction through a pipeline of the integrated circuit. Various other devices, systems, and methods are also disclosed.
    Type: Application
    Filed: December 22, 2023
    Publication date: June 26, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Heather Lynn Hanson, Yasuko Eckert, Onur Kayiran, Gabriel H. Loh, Travis Boraten, Bradford Beckmann
  • Publication number: 20250210417
    Abstract: A method includes forming a plurality of thermal sensing elements at predetermined locations on a semiconductor chip proximate to a target location, measuring a temperature of the semiconductor chip at each predetermined location using a corresponding one of the plurality of thermal sensing elements, and determining a temperature at the target location using the temperatures measured at each of the predetermined locations.
    Type: Application
    Filed: December 22, 2023
    Publication date: June 26, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Gabriel H. Loh, Thomas D. Burd
  • Publication number: 20250205606
    Abstract: A technique includes determining a base decision rate; monitoring for key events; and based on the base decision rate and the monitoring, determining a time at which to generate an action to be performed by an application entity of an application. The base decision rate includes a baseline rate at which the application is directed to determine new actions to be performed by the application entity. In some examples, the base decision rate is determined using a trained AI model, by applying information about the state of the application to the model and obtaining the base decision rate in response. In some examples, key events are unexpected events that occur in the application. In some examples, since the base decision rate represents a rate at which to generate actions, given the current state of the application, the key events, which represent unexpected events, override or modify the base decision rate.
    Type: Application
    Filed: December 22, 2023
    Publication date: June 26, 2025
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Alexander Walter Cann, Ian Charles Colbert, Zachariah Louis Vincze, Mehdi Saeedi
  • Publication number: 20250210600
    Abstract: A system-on-chip structure includes a substrate, first and second die disposed over a surface of the substrate and separated by an inter-die gap, a protection layer disposed over a sidewall of each of the first and second die, and a gap fill layer disposed over the protection layers and substantially filling the inter-die gap.
    Type: Application
    Filed: December 22, 2023
    Publication date: June 26, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Hsiang-Wei Liu
  • Publication number: 20250211215
    Abstract: Methods of fabricating a semiconductor device include securing a first die to a second die. The first die includes a first clock signal path from a clock source to a first load and passing through a tap point electrically connected to a clock output. The second die includes a second clock signal path from a clock input to a second load. The methods also include connecting the clock input of the second die to the clock output of the first die. A first divergence between the tap point and the first load is substantially the same as a second divergence from the tap point through the clock input and the clock output to the second load. Various other methods, devices, and systems are also disclosed.
    Type: Application
    Filed: December 22, 2023
    Publication date: June 26, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Shravan Lakshman, Sudarshan Selvarajan, Russell Schreiber
  • Publication number: 20250208878
    Abstract: A technique is provided. The technique includes opening an aperture for processing partial results; receiving partial results in the aperture; and processing the partial results to generate final results.
    Type: Application
    Filed: December 20, 2023
    Publication date: June 26, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Nicholas Patrick Wilt
  • Publication number: 20250208922
    Abstract: A technique for controlling processing precision is provided. The technique includes identifying a first set of execution instances to operate at a normal precision and a second set of execution instances to operate at a reduced precision; and operating the first set of execution instances at the normal precision and the second set of execution instances at the reduced precision.
    Type: Application
    Filed: December 21, 2023
    Publication date: June 26, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventor: Yu Ma
  • Publication number: 20250210538
    Abstract: An exemplary apparatus for uniquely identifying individual dies across die stacks includes a die stack and a plurality of signals arranged across the die stack. The plurality of signals are manipulated to form a unique identifier for each die included in the die stack. Various other apparatuses, systems, and methods are also disclosed.
    Type: Application
    Filed: December 22, 2023
    Publication date: June 26, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Richard Martin Born, John Wuu
  • Publication number: 20250208681
    Abstract: The disclosed device includes various components; and a control circuit for managing performance states of the components. The control circuit can receive an event trigger corresponding to one of the components, monitor an activity metric for the component, and update a performance state of the component based on the event trigger and the activity metric. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: May 26, 2023
    Publication date: June 26, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Heather Lynn Hanson, Yasuko Eckert, Rajagopalan Desikan, Satvik Maurya
  • Publication number: 20250208875
    Abstract: Devices, methods, and systems for load fusion. In an explicit approach, a first load operation and a second load operation, in a stream of operations, are replaced with a single load operation. One or more operations, configured to move and shift a value stored in a destination register of the single load operation, are inserted after the single load operation in the stream of operations. In an implicit approach, Information of a first load operation is inserted into a tracking table. Information of a second load operation is inserted into the tracking table responsive to an address of the second load operation being within a range. A load operation is executed from an address indicated by the first load operation and from an address indicated by the second load operation based on the tracking table.
    Type: Application
    Filed: December 21, 2023
    Publication date: June 26, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Alexander Toufic Freij, Matthew Raymond Poremba, Gabriel H. Loh, Onur Kayiran
  • Publication number: 20250209006
    Abstract: A technique for improving performance of a hash operation on a processor is provided, in which an input value is hashed into a second value corresponding to a number of bins. The number of bins is an integer that corresponds to a product of first and second integers, the first integer corresponding to a prime number and the second integer corresponding to a power of two. A first modulo hashing operation is performed in which the input value is hashed into the first integer. A second hashing operation is performed using less than all bits of the input value. An output value is formed by concatenating a result of the first hashing operation with a result of the second hashing operation.
    Type: Application
    Filed: December 20, 2023
    Publication date: June 26, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Jeffrey Christopher Allan, Mark Leather
  • Publication number: 20250208979
    Abstract: Devices, methods, and systems for communicating debugging information. Debugging information is stored from debugging hardware of an integrated circuit into a memory of the integrated circuit. The debugging information is retrieved from the memory and encapsulating the debugging information in a packet. The packet is transmitted over an interface to a device that is external to the integrated circuit. In some implementations, the debugging information is stored in MMIO space of the memory that is not mapped to registers of the integrated circuit. In some implementations, the debugging information is stored in a MMIO space of the memory, wherein a base address of the MMIO is indicated in a base address register (BAR) of the integrated circuit. In some implementations, the debugging information is encapsulated in a USB4 packet and transmitted over a USB4 interface to the device that is external to the integrated circuit.
    Type: Application
    Filed: December 20, 2023
    Publication date: June 26, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Kong Ling, Paul A. Simoncic, Jagadish Hadimani
  • Publication number: 20250209721
    Abstract: A technique for rendering is provided. The technique includes mapping a randomization portion of an item of identifying information to a random block of an address space; mapping a linear portion of the item of identifying information to an element within the block; and accessing the element.
    Type: Application
    Filed: December 20, 2023
    Publication date: June 26, 2025
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Michal Adam Wozniak, Guennadi Riguer
  • Publication number: 20250210557
    Abstract: A bonded die assembly includes first conductive pads of a first substrate each bonded to respective second conductive pads of a second substrate, the first and second conductive pads arrayed at an inter-pad spacing, a plurality of active components located in the second substrate and arrayed at an inter-component spacing, and a metallization structure disposed between the first substrate and the second substrate, where the metallization structure is configured to decrease the inter-component spacing relative to the inter-pad spacing. The die assembly is characterized by an improved utilization of available device active area.
    Type: Application
    Filed: December 22, 2023
    Publication date: June 26, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Darryl Prudich, Carson Donahue Henrion, Eric Busta, John Wuu, Russell Schreiber, Stephen Dussinger
  • Publication number: 20250208990
    Abstract: A data processing system includes a data processor and a memory. The data processor is for issuing memory commands including a first memory command that accesses data of a first size. The memory is operative to transfer data of the first size by separating a first portion of data from a second portion of data by a data gap. The data processor is operable to selectively prioritize and issue a second memory command after issuing the first memory command at a time that fills the data gap.
    Type: Application
    Filed: December 21, 2023
    Publication date: June 26, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Tahsin Askar, James R. Magro
  • Publication number: 20250209005
    Abstract: The disclosed computer-implemented method includes configuring a cache with a cache addressing scheme that increases a capacity of each entry of the cache, compressing a data segment for storing in the cache, and storing metadata of the compression in the cache with the compressed data segment. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Application
    Filed: December 28, 2022
    Publication date: June 26, 2025
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Gregg Donley, Chintan S. Patel, Vydhyanathan Kalyanasundharam