Abstract: A data processing system includes a data processor and a memory. The data processor is for issuing memory commands including a first memory command that accesses data of a first size. The memory is operative to transfer data of the first size by separating a first portion of data from a second portion of data by a data gap. The data processor is operable to selectively prioritize and issue a second memory command after issuing the first memory command at a time that fills the data gap.

Abstract: In accordance with the described techniques, a device includes a memory system and a processor communicatively coupled to the memory system. The processor receives a load instruction from the memory system instructing the processor to load data associated with an address. In response, the processor performs a lookup for the address in a bloom filter that tracks zero value cache lines that have previously been accessed. Based on the lookup indicating that a hash of the address is present in the bloom filter, the processor generates zero value data. Furthermore, the processor processes one or more dependent instructions using the zero value data.

Abstract: A memory request issue counter (MRIC) is maintained that is incremented for every memory access a central processing unit core makes. A region reuse distance table is also maintained that includes multiple entries each of which stores the region reuse distance for a corresponding region. When a memory access request for a physical address is received, a reuse distance for the physical address is calculated. This reuse distance is the difference between the current MRIC value and a previous MRIC value for the physical address. The previous MRIC value for the physical address is the MRIC value the MRIC had when a memory access request for the physical address was last received. A region reuse distance for a region that includes the physical address is generated based on the reuse distance for the physical address and used to manage the cache.

Abstract: Methods, apparatuses, and computer-readable medium for incorporating motion awareness into the decision-making process of automatic exposure (AE) to prevent noticeable image quality deterioration resulting from motion blur. In some instances, by harnessing the capabilities of integrated camera Image Signal Processors (ISP), Inference Processing Unit (IPU), and/or Artificial Intelligent (AI) acceleration, the described methods, apparatuses, and computer-readable medium may achieve optimal computational efficiency and enhanced image quality.

Abstract: An exemplary apparatus for distributing die-specific signals across die stacks includes a die stack and a plurality of signals arranged in a sequence across the die stack. The plurality of signals shift positions in the sequence between a first die and a second die included in the die stack. Various other apparatuses, systems, and methods are also disclosed.

Abstract: Devices and methods for allocating components of a safety critical system are provided. The processing device comprises resources including memory, a host processor and a plurality of processors connected to the resources via a shared pathway of a network and configured to execute an application based on instructions from the host processor. Each of the plurality of processors is assigned to one of a plurality of criticality domain levels and isolated pathways are created, via the shared pathway, between the plurality of processors and the plurality of resources based on which of the processors are assigned to one or more of the plurality of criticality domain levels to access one or more of the plurality of resources. The application is executed using the network. The isolated pathways are, for example, created by disabling one or more switches. Alternatively, the isolated pathways are created via programmable logic.

Abstract: The disclosed computer-implemented apparatus for bridge-based packaging with direct power delivery can include an first layer stacked on a second layer. The second layer can include an interposer die and a connection die. The first layer can include a chiplet die positioned above the interposer die and a first-layer bridge die spanning across the interposer die and the connection die. The interposer die can include a set of physical interfaces and a set of routing features configured to route signals from the set of physical interfaces to the first-layer bridge die. Various other apparatuses, systems, and methods of manufacture are also disclosed.

Abstract: A technique for performing a path tracing operation is provided. A cache is interrogated using a probe operation that returns a Boolean result for each of a plurality of scene data elements associated with the path tracing operation. The Boolean result indicates presence or absence of a scene data element in the cache. The path tracing operation executes at least a first instruction based at least in part on the probe operation returning a Boolean result indicating absence of one of the scene data elements in the cache. The path tracing operation executes at least a second instruction based at least in part on the probe operation returning a Boolean result indicating presence of said one scene data element in the cache, wherein the first instruction is different from the second instruction.

Abstract: A cache cleaner controller is described. In one or more examples, an apparatus includes a cache directory including status bits associated with cache locations within cache storage and a cache cleaner controller. The cache cleaner controller is configured to detect that a cache cleaner threshold has been reached. The cache cleaner threshold defines that a threshold number of the status bits indicate data maintained at the cache locations, respectively, has been changed. The cache cleaner controller is also configured to cause the data indicated as changed by the status bits to be copied from the cache locations within cache storage to the physical volatile memory.

Abstract: Matrix-fused min-add (MFMA) instructions are described. The MFMA instructions cause a processing device to execute at least one of a min-plus function or a plus-min function. The MFMA instructions cause the processor device to execute min-plus and plus-min functions in response to a single instruction and without performing a multiplication operation as required by conventional systems. In accordance with the described techniques, a MFMA instruction causes multiple logic units (e.g., threads or wavefronts) of a processing device to execute a min-plus function, a plus-min function, or combinations thereof, as part of completing a computational task. To optimize system efficiency, the MFMA instruction causes the processing device to execute the min-plus function, the plus-min function, or combinations thereof using data stored in local registers of the processor device.

Abstract: Systems, apparatuses, and methods for reducing probe filter accesses in response to processing-in-memory (PIM) requests are disclosed. A coherent secondary unit receives PIM requests targeting a corresponding PIM device. For each PIM request that is received, the coherent secondary unit performs a lookup of a PIM address table (PAT). If the address of the PIM request matches an address of an existing entry in the PAT, the coherent secondary unit prevents the PIM request from being sent to a probe filter. Otherwise, if there is no match for the address of the PIM request in the entries of the PAT, the coherent secondary unit sends the PIM request to the probe filter, and the coherent secondary unit creates a new PAT entry for the address of the PIM request. Any subsequent PIM requests to the same address will match with the new entry in the PAT.

Abstract: An approach is provided for managing near-memory processing commands (“PIM commands”) from multiple processor threads in a manner to prevent interference and maintain correctness at near-memory processing elements. A memory controller uses thread identification information and last command information to issue a PIM command sequence from a first processor thread, directed to a PIM-enabled memory element, while deferring the issuance of PIM command sequences from other processor threads, directed to the same PIM-enabled memory element. After the last PIM command in the PIM command sequence for the first processor thread has been issued, a PIM command sequence for another processor thread is issued, and so on. The approach allows multiple processor threads to concurrently issue fine grained PIM commands to the same PIM-enabled memory element without having to be aware of address-to-memory element mapping, and without having to coordinate with other threads.

Abstract: A coprocessor such as a floating-point unit includes a pipeline that is partitioned into a first portion and a second portion. A controller is configured to provide control signals to the first portion and the second portion of the pipeline. A first physical distance traversed by control signals propagating from the controller to the first portion of the pipeline is shorter than a second physical distance traversed by control signals propagating from the controller to the second portion of the pipeline. A scheduler is configured to cause a physical register file to provide a first subset of bits of an instruction to the first portion at a first time. The physical register file provides a second subset of the bits of the instruction to the second portion at a second time subsequent to the first time.

Abstract: The disclosed semiconductor package includes a first chiplet area for receiving a first chiplet, a second chiplet area for receiving a second chiplet, and a host die coupled to the first and second chiplet areas. The semiconductor package also includes an interconnect directly coupling the first chiplet area to the second chiplet area. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A data processor is adapted to couple to a memory. The data processor includes a memory operation array, a power engine, and an initialization circuit. The memory operation array includes a command portion and a data portion. The power engine has an input for receiving power state change request signals and an output for providing memory operations responsive to instructions stored in the command portion. The initialization circuit populates the data portion such that consecutive memory operations are separated by an amount corresponding to a predetermined minimum timing parameter.

Abstract: According to one aspect, a system includes a processor core, a history buffer, a history buffer logic, and an interrupt controller. The processor core is configured to issue a trigger that causes the history buffer logic to, after a fixed time, flush existing entries in the history buffer and start adding new entries into the history buffer. According to another aspect, a system includes a processor core that includes a load store tracker buffer and a prefetch engine. The buffer is configured to track a critical section memory location associated with critical section data fetched by the processor core. The prefetch engine is configured to obtain the critical section memory location from a previous load store tracker buffer associated with a previous lock holder processor core. The system also includes a lock manager configured to signal the buffer to start and stop tracking the critical section memory.

Abstract: A disclosed method may include initializing a deep learning recommendation model (DLRM) comprising a plurality of embedding tables, each embedding table comprising a plurality of embeddings. The method may also include receiving input data associated with accessing embeddings from the plurality of embedding tables and applying a parallelization strategy to process the plurality of embedding tables, the parallelization strategy configured to improve performance by distributing computational workloads and optimizing memory access. The method may also include processing the embeddings based on the input data in accordance with the parallelization strategy, the processing comprising aggregating embeddings accessed from the plurality of embedding tables. The method may also include generating, for further processing, output data based on the processed embeddings. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: The disclosed device includes multiple physical processor cores including enabled cores and disabled cores. The device also includes a controller that can track a total aging value for each core and facilitate swapping out enabled cores for disabled cores to manage core lifespans. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: An example system includes a plurality of wait queues implemented in a first portion of a memory unit configured to store a plurality of lock requests. The system includes a lock head array implemented in a second portion of the memory unit configured to store a plurality of lock heads. Each wait queue of the plurality of wait queues is mapped to one lock head in the lock head array. The system includes a lock waiter array implemented in a third portion of the memory unit configured to store a number of entries corresponding to each lock head in the lock head array. The system also includes a spinlock controller including hardware circuitry configured to execute a lock logic responsive to a lock acquire request of the plurality of lock requests, and to execute an unlock logic responsive to a lock release request of the plurality of lock requests.

Abstract: The disclosed device can include a dual-tail sampler. The dual-tail sampler can include a first stage with an input pair, a cross-coupled load circuit, a precharge device between drain nodes of the input pair, and at least one pass-gate switch between the input pair and the cross-coupled load circuit. Various other devices and systems are also disclosed.