Abstract: Methods and systems are described. A system includes a redundant shader pipe array that performs rendering calculations on data provided thereto and a shader pipe array that includes a plurality of shader pipes, each of which performs rendering calculations on data provided thereto. The system also includes a circuit that identifies a defective shader pipe of the plurality of shader pipes in the shader pipe array. In response to identifying the defective shader pipe, the circuit generates a signal. The system also includes a redundant shader switch. The redundant shader switch receives the generated signal, and, in response to receiving the generated signal, transfers the data for the defective shader pipe to the redundant shader pipe array.

Abstract: An approach is provided for implementing memory profiling aggregation. A hardware aggregator provides memory profiling aggregation by controlling the execution of a plurality of hardware profilers that monitor memory performance in a system. For each hardware profiler of the plurality of hardware profilers, a hardware counter value is compared to a threshold value. When a threshold value is satisfied, execution of a respective hardware profiler of the plurality of hardware profilers is initiated to monitor memory performance. Multiple hardware profilers of the plurality of hardware profilers may execute concurrently and each generate a result counter value. The result counter values generated by each hardware profiler of the plurality of hardware profilers are aggregated to generate an aggregate result counter value. The aggregate result counter value is stored in memory that is accessible by a software processes for use in optimizing memory-management policy decisions.

Abstract: A system and method for controlling characteristics of collected image data are disclosed. The system and method include performing pre-processing of an image using GPUs, configuring an optic based on the pre-processing, the configuring being designed to account for features of the pre-processed image, acquiring an image using the configured optic, processing the acquired image using GPUs, and determining if the processed acquired image accounts for feature of the pre-processed image, and the determination is affirmative, outputting the image, wherein if the determination is negative repeating the configuring of the optic and re-acquiring the image.

Abstract: An arithmetic unit performs store-to-load forwarding based on predicted dependencies between store instructions and load instructions. In some embodiments, the arithmetic unit maintains a table of store instructions that are awaiting movement to a load/store unit of the instruction pipeline. In response to receiving a load instruction that is predicted to be dependent on a store instruction stored at the table, the arithmetic unit causes the data associated with the store instruction to be placed into the physical register targeted by the load instruction. In some embodiments, the arithmetic unit performs the forwarding by mapping the physical register targeted by the load instruction to the physical register where the data associated with the store instruction is located.

Abstract: Improvements in the graphics processing pipeline are disclosed. More specifically, a new primitive shader stage performs tasks of the vertex shader stage or a domain shader stage if tessellation is enabled, a geometry shader if enabled, and a fixed function primitive assembler. The primitive shader stage is compiled by a driver from user-provided vertex or domain shader code, geometry shader code, and from code that performs functions of the primitive assembler. Moving tasks of the fixed function primitive assembler to a primitive shader that executes in programmable hardware provides many benefits, such as removal of a fixed function crossbar, removal of dedicated parameter and position buffers that are unusable in general compute mode, and other benefits.

Abstract: A rendering processor assigns varying logical pixel dimensions to regions of an image frame and rendering pixels of the image frame based on the logical pixel dimensions. The rendering processor renders in highest resolution (i.e., with smaller logical pixel dimensions) those areas of the image that are more important (on which the viewer is expected to focus (the “foveal region”), or regions with little-to-no motion), and renders in lower resolution (i.e., with larger logical pixel dimensions) those areas of the image outside the region of interest, or regions that are speedily moving, so that loss of detail in those regions will be less noticeable to the viewer. For regions with less detail or greater magnitude of motion, larger logical pixel dimensions reduce the computational workload without affecting the quality of the displayed graphics as perceived by a user.

Abstract: A memory controller includes an address decoder, a first command queue coupled to a first output of the address decoder for receiving memory access requests for a first memory channel, and the second command queue coupled to a second output of the address decoder for receiving memory access requests for a second memory channel. A request credit control circuit is coupled to the first command queue and the second command queue, and operates to track a number of outstanding request credits. The request credit control circuit issues a request credit in response to a designated event based on a number of available entries of the first and second command queues.

Abstract: An integrated circuit includes a plurality of tiles receiving a power supply voltage, each having a corresponding analog circuit and operates in response to a first voltage, and a hardware controller receiving a voltage identification code and provides the first voltage to each of the plurality of tiles in response thereto. The hardware controller comprises a test time controller determining coefficients of a waveform that describes an average correspondence between the power supply voltage and the first voltage for the plurality of tiles, and a boot time controller determining a respective error signal indicating an error between the waveform and a respective actual waveform for each of the plurality of tiles, and providing the respective error signal to the corresponding analog circuit of each of the plurality of tiles. The corresponding analog circuit of each of the plurality of tiles adjusts the first voltage according to the respective error signal.

Abstract: Methods and devices are provided for processing image data on a sub-frame portion basis using layers of a convolutional neural network. The processing device comprises memory and a processor. The processor is configured to receive frames of image data comprising sub-frame portions, schedule a first sub-frame portion of a first frame to be processed by a first layer of the convolutional neural network when the first sub-frame portion is available for processing, process the first sub-frame portion by the first layer and continue the processing of the first sub-frame portion by the first layer when it is determined that there is sufficient image data available for the first layer to continue processing of the first sub-frame portion. Processing on a sub-frame portion basis continues for subsequent layers such that processing by a layer can begin as soon as sufficient data is available for the layer.

Abstract: Data processing methods and devices are provided. A processing device comprises memory and a processor. The memory, which comprises a cache, is configured to store portions of data. The processor is configured to issue a store instruction to store one of the portions of data, provide identifying information associated with the one portion of data, compress the one portion of data; and store the compressed one portion of data across multiple lines of the cache using the identifying information. In an example, the one portion of data is a block of pixels and pixels and the processor is configured to request pixel data for a pixel of a compressed block of pixels, send additional requests for data for other pixels determined to belong to the compressed pixel block and provide an indication that the requests are for pixel data belonging to the compressed block of pixels.

Abstract: Methods and processing devices are provided for error protection to support instruction replay for executing idempotent instructions at a processing in memory PIM device. The processing apparatus includes a PIM device configured to execute an idempotent instruction. The processing apparatus also includes a processor, in communication with the PIM device, configured to issue the idempotent instruction to the PIM device for execution at the PIM device and reissue the idempotent instruction to the PIM device when one of execution of the idempotent instruction at the PIM device results in an error and a predetermined latency period expires from when the idempotent instruction is issued.

Abstract: A method and processing apparatus are provided for executing a program. The processing apparatus comprises memory and a processor. The processor is configured to dispatch a parent work group of a program to be executed and execute a spawn work group instruction to enable a child work group of the parent work group to be executed. The processor is also configured to dispatch the child work group for execution when a sufficient amount of resources are determined to be available to execute the child work group and execute the child work group on one or more compute units. The spawn work group instruction comprises a pointer to a synchronization variable, and the processor is also configured to execute a join workgroup instruction which comprises the pointer to the synchronization variable in the spawn work group instruction.

Abstract: Memories that are configurable to operate in either a banked mode or a bit-separated mode. The memories include a plurality of memory banks; multiplexing circuitry; input circuitry; and output circuitry. The input circuitry inputs at least a portion of a memory address and configuration information to the multiplexing circuitry. The multiplexing circuitry generates read data by combining a selected subset of data corresponding to the address from each of the plurality of memory banks, the subset selected based on the configuration information, if the configuration information indicates a bit-separated mode. The multiplexing circuitry generates the read data by combining data corresponding to the address from one of the memory banks, the one of the memory banks selected based on the configuration information, if the configuration information indicates a banked mode. The output circuitry outputs the generated read data from the memory.

Abstract: Systems and methods related to encoding metadata or other status information into error correcting code (ECC) for a data block. In one embodiment, an encoder of a memory controller generates ECC check bits based on a data block and virtual bits representing metadata, then stores the ECC check bits and the data block as a code word. Subsequently, multiple decoders of the memory controller process candidate code words that include the code word and candidate virtual bit values to detect errors in the candidate code words. The decoders output signals identifying each candidate code word as having no error, a correctable error, or an uncorrectable error and outputs a calculated error location in the case of a correctable error. The system determines the actual value of the virtual bits based on the outputs of the decoders and corrects any identified correctable error in the recovered code word.

Abstract: Systems, devices, and methods for direct memory access. A system direct memory access (SDMA) device disposed on a processor die sends a message which includes physical addresses of a source buffer and a destination buffer, and a size of a data transfer, to a data fabric device. The data fabric device sends an instruction which includes the physical addresses of the source and destination buffer, and the size of the data transfer, to first agent devices. Each of the first agent devices reads a portion of the source buffer from a memory device at the physical address of the source buffer. Each of the first agent devices sends the portion of the source buffer to one of second agent devices. Each of the second agent devices writes the portion of the source buffer to the destination buffer.

Abstract: A system and method for providing for adoption of solvers for solving at least one task is disclosed. The system and method include a controller, solvers capable of solving the at least one task, and at least one memory. The controller admits ones of the solvers into a competition for solving the at least one task, provides, via the at least one memory, an input of the task to the admitted solvers, provides, via the at least one memory, intermediate results of execution by the admitted solvers that are provided the input, receives a prediction of the next intermediate result from the admitted solvers predicting from at least one of the provided input and received intermediate results, and ranks the at least one of the admitted solvers for solving the task based on at least one of the next intermediate results, the provided input and received intermediate results.

Abstract: An image processing method and an image processing device is provided. The processing device comprises memory and a processor configured to receive a frame of color filtered image data comprising pixels which are spatially multiplexed according to a plurality of different light exposures, resample the color values as different frames of pixels for the plurality of different light exposures, fuse the resampled frames of pixels for the plurality of different light exposures into a frame of pixels according to a HDR format and color interpolate the fused frame of pixels. The processor is configured to interpolate, for each resampled frame, missing pixel color values based on the color values of adjacent resampled pixels in a same resampled frame. The color interpolated fused frame of pixels is processed in an image processing pipeline and converted to a YUV color space.

Abstract: Methods, devices, and systems for launching a compute kernel. A reference kernel dispatch packet is received by a kernel agent. The reference kernel dispatch packet is processed by the kernel agent to determine kernel dispatch information. The kernel dispatch information is stored by the kernel agent. A kernel is dispatched by the kernel agent, based on the kernel dispatch information. In some implementations, a condensed kernel dispatch packet is received by the kernel agent, the condensed kernel dispatch packet is processed by the kernel agent to retrieve the stored kernel dispatch information, and a kernel is dispatched by the kernel agent based on the retrieved kernel dispatch information.

Abstract: Techniques for identifying a hardware configuration for operation are disclosed. The techniques include applying feature measurements to a trained model; obtaining output values from the trained model, the output values corresponding to different hardware configurations; and operating according to the output values, wherein the output values include one of a certainty score, a ranking, or a regression value.

Abstract: A method and system for memory attack mitigation in a memory device includes receiving, at a memory controller, an allocation of a page in memory. One or more device controllers detects an aggressor-victim set within the memory. Based upon the detection, an address of the allocated page is identified for further action.