Abstract: A technique for performing ray tracing operations is provided. The technique includes performing bounding volume hierarchy (“BVH”) traversal in multiple accelerated processing devices (“APDs”), utilizing bounding volume hierarchy data copies in memories local to the multiple APDs; rendering primitives determined to be intersected based on the BVH traversal, using geometry information and texture data spread across the memories local to the multiple APDs; and storing results of rendered primitives for a set of tiles assigned to the multiple APDs into tile buffers stored in APD memories local to the APDs.

Abstract: A method and apparatus of protecting a memory from a write attack includes dividing a cacheline of memory into a plurality of sub-blocks. A codeword is generated from at least one sub-block of the plurality of sub-blocks and a complement of the at least one sub-block. One of the generated codewords is selected, wherein the selected codeword is used for storage in memory.

Abstract: A circuit and method are provided to monitor a clock for a data processor. The method includes receiving a clock signal and producing a first voltage proportional to a frequency of the clock signal. The first voltage is converted to a digital signal. During an initialization mode, the method ensures the clock signal is at a desired frequency and scales the digital signal using a first configurable ratio to produce a high threshold value. When changing from the initialization mode to an operating mode, the method ceases to scale the digital signal and maintains the high threshold value. During the operating mode, the method compares the digital signal to the high threshold value to determine if the clock signal has been increased in frequency beyond a desired level, and if so, triggers an overclock alert to a system management circuit of the data processor.

Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package includes a package substrate that has a first side and a second side opposite to the first side. A semiconductor chip is mounted on the first side. Plural metal anchor structures are coupled to the package substrate and project away from the first side. A molding layer is on the package substrate and at least partially encapsulates the semiconductor chip and the anchor structures. The anchor structures terminate in the molding layer and anchor the molding layer to the package substrate.

Abstract: A method and system for recording and logging errors in a computer system includes reading first error handling information with respect to a transaction. The first error handling information is stored in a first component, and based upon a condition of the storage in the first component, an oldest error information is evicted from the first component.

Abstract: The low end operating voltage of an integrated circuit is adjusted. Oscillations are counted at a ring oscillator on the integrated circuit over a designated period of clock cycles. Based on the number of oscillations, a prediction model associated with a first set of device degradation data and a second set of static random-access memory (SRAM) low end operating voltage data is used to select a low end operating voltage limit for a processor on the integrated circuit. The low end operating voltage of the processor is set based on the selected low end operating voltage limit. These steps are repeated multiple times during operation of the processor. A method of testing integrated circuits to provide the data employed to produce the prediction model is also provided.

Abstract: A uniform cache system and method for fast data access are disclosed. The system and method include a plurality of compute units (CUs) and a plurality of L0 caches. The plurality of CUs and the plurality of L0 caches are arranged in a network configuration where each one of the plurality of CUs is surrounded by a first group of the plurality of L0 caches and each of the plurality of L0 caches is surrounded by a L0 cache group and CU group. Operationally, ones of the plurality of CUs, upon a request for data, queries the surrounding first group of the plurality of L0 caches to satisfy the request. On a condition that the first group of the plurality of L0 caches fails to satisfy the data request, each of the first group of the plurality of L0 caches query a second group of adjacent L0 caches to satisfy the request. On a condition that the second group of adjacent L0 caches fails to satisfy the data request, each of the second group of adjacent L0 caches propagating the query to the next group of L0 caches.

Abstract: Methods, devices, and systems for information communication. Information transmitted from a host to a graphics processing unit (GPU) is received by information analysis circuitry of a field-programmable gate array (FPGA). A pattern in the information is determined by the information analysis circuitry. A predicted information pattern is determined, by the information analysis circuitry, based on the information. An indication of the predicted information pattern is transmitted to the host. Responsive to a signal from the host based on the predicted information pattern, the FPGA is reprogrammed to implement decompression circuitry based on the predicted information pattern. In some implementations, the information includes a plurality of packets. In some implementations, the predicted information pattern includes a pattern in a plurality of packets. In some implementations, the predicted information pattern includes a zero data pattern.

Abstract: Techniques for performing ray tracing operations are provided. The techniques include dividing a primitive of a scene to generate primitive portions; identifying, from the primitive portions, and based on an opacity texture, one or more opaque primitive portions and one or more invisible primitive portions; generating box nodes for a bounding volume hierarchy corresponding to the opaque primitive portions, but not the invisible primitive portions; and inserting the generated box nodes into the bounding volume hierarchy.

Abstract: A memory controller interfaces with a dynamic random access memory (DRAM). The memory controller selectively places memory commands in a memory interface queue and transmits the memory commands from the memory interface queue to a memory channel coupled to at least one dynamic random access memory (DRAM). An activate counter is maintained related to a number of activate commands sent over the memory channel to a memory region of the DRAM. In response to the activate counter being at or above a designated threshold, an arbiter is signaled that a refresh command should be sent to the memory region. In response to a designated condition, a value of the activate counter is adjusted by a total number based on a first fixed number and second varying number selected with one of random selection and pseudo-random selection.

Abstract: A processor adjusts the voltage margin of a supply voltage based on a sampled clock frequency. The processor generates the supply voltage by combining the voltage margin with a specified nominal voltage, and provides the supply voltage to a processor module, such as graphics processing unit (GPU). In addition, an adaptive clock module (e.g., a digital frequency-locked loop) generates a clock signal for the processor module, wherein the frequency of the clock signal varies at least in part based on the supply voltage. The processor samples the frequency of the clock signal and adjusts the voltage margin based on the sampled frequency. The processor thereby keeps excursions in the clock frequency within a specified limit, thus supporting a relatively stable clock frequency.

Abstract: A method of dynamic cache configuration includes determining, for a first clustering configuration, whether a current cache miss rate exceeds a miss rate threshold. The first clustering configuration includes a plurality of graphics processing unit (GPU) compute units clustered into a first plurality of compute unit clusters. The method further includes clustering, based on the current cache miss rate exceeding the miss rate threshold, the plurality of GPU compute units into a second clustering configuration having a second plurality of compute unit clusters fewer than the first plurality of compute unit clusters.

Abstract: Entropy agnostic data encoding includes: receiving, by an encoder, input data including a bit string; generating a plurality of candidate codewords, including encoding the input data bit string with a plurality of binary vectors, wherein the plurality of binary vectors includes a set of deterministic biased binary vectors and a set of random binary vectors; selecting, in dependence upon a predefined criteria, one of the plurality of candidate codewords; and transmitting the selected candidate codeword to a decoder.

Abstract: A data processor includes at least one power supply voltage terminal for receiving a power supply voltage and a power supply current, a data processing circuit, a register, and a port controller. The data processing circuit is coupled to the at least one power supply voltage terminal and operates using the power supply voltage. The register stores a nominal value of the power supply voltage, an electrical design current (EDC) limit, and an EDC slope, wherein the EDC slope specifies a desired voltage-current relationship for an external voltage regulator when the power supply current exceeds the EDC limit. The port controller is coupled to the register and to an output port. The data processing circuit is operative to cause the port controller to output the nominal value of the power supply voltage, the EDC limit, and the EDC slope over the output port for use by the external voltage regulator.

Abstract: A processing system reduces by staging precharging of bitlines of a memory. In a static random access memory (SRAM) array, the voltage level on every bitline in the array is precharged to a reference voltage (VDD) rail voltage before a memory access. To facilitate reduction of current spikes from precharging, a precharge control unit groups entries of a RAM into a plurality of subsets, or regions, and applies a different precharge signal for precharging bitlines associated with each subset. Application of the precharge signals to the respective subsets over time results in smaller current spikes than simultaneous application of precharge signals to all of the bitlines.

Abstract: Methods and apparatuses are disclosed herein for performing tone mapping and/or contrast enhancement. In some examples, a block mapping curve is low-pass filtered with block mapping curves of surrounding blocks to form a smoothed block mapping curve. In some examples, overlapped curve mapping of block mapping curves, including smoothed block mapping curves, is performed, including weighting, based on a pixel location, block mapping curves of a group of blocks to generate an interpolated block mapping curve and applying the interpolated block mapping curve to a pixel to perform ton mapping and/or contrast enhancement.

Abstract: A technique for accessing accelerated processing device (“APD”) memory is provided. The technique includes identifying whether to activate one or both of a first direct mapping unit and a second direct mapping unit, wherein the first direct mapping unit is associated with a small address size and the second direct mapping unit is associated with a large address size; activating the identified one or both of the first direct mapping unit and the second direct mapping unit; and accessing memory of the accelerated processing device using the one or both of the first direct mapping unit and the second direct mapping unit.

Abstract: Methods and apparatuses are disclosed herein for performing tone mapping and/or contrast enhancement. In some examples, a block mapping curve is low-pass filtered with block mapping curves of surrounding blocks to form a smoothed block mapping curve. In some examples, overlapped curve mapping of block mapping curves, including smoothed block mapping curves, is performed, including weighting, based on a pixel location, block mapping curves of a group of blocks to generate an interpolated block mapping curve and applying the interpolated block mapping curve to a pixel to perform ton mapping and/or contrast enhancement.

Abstract: An electronic device includes a die stack having a plurality of die. The die stack includes a die parity path spanning the plurality of die and configured to alternatingly identify each die as a first type or a second type. The die stack further includes an inter-die signal path spanning the plurality of die and configured to propagate an inter-die signal through the plurality of die, wherein the inter-die signal path is configured to invert a logic state of the inter-die signal between each die. Each die of the plurality of die includes signal formatting logic configured to selectively invert a logic state of the inter-die signal before providing it to other circuitry of the die responsive to whether the die is designated as the first type or the second type.

Abstract: Described herein are techniques for executing a heterogeneous code object executable. According to the techniques, a loader identifies a first memory appropriate for loading a first architecture-specific portion of the heterogeneous code object executable, wherein the first architecture specific portion includes instructions for a first architecture, identifies a second memory appropriate for loading a second architecture-specific portion of the heterogeneous code object executable, wherein the second architecture specific portion includes instructions for a second architecture that is different than the first architecture, loads the first architecture-specific portion into the first memory and the second architecture-specific portion into the second memory, and performs relocations on the first architecture-specific portion and on the second architecture-specific portion.