Abstract: Enhanced methods for memory context restore are described. A device may include a physical layer (PHY) having an interface to support communication of command signals and data with a physical memory. The PHY implements a training mode to train the interface, detect values of a plurality of parameters as part of training the interface, and store the detected values as initial training data. The PHY also implements a retraining mode to use the initial training data as seed data to retrain the interface.

Abstract: A data processor that is operable to be coupled to a memory includes a memory operation array, a controller, a refresh logic circuit, and a selector. The memory operation array is for storing memory operations for a first power state of the memory. The controller is responsive to a power state change request to execute a plurality of memory operations from the memory operation array when the first power state is selected. The refresh logic circuit generates refresh cycles periodically for the memory. The selector is for multiplexing the refresh cycles with the memory operations during a power state change to the first power state.

Abstract: An accelerated processing device is provided which comprises a plurality of compute units each including a plurality of SIMD units, and each SIMD unit comprises a register file. The accelerated processing device also comprises LDS in communication with each of the SIMD units. The accelerated processing device also comprises a first portion of cache memory, in communication with each of the SIMD units and a second cache portion of memory shared by the compute units. The compute units are configured to execute a program in which a storage portion of at least one of the register file of a SIMD unit, the first portion of cache memory and the LDS is reserved as part of another of the register file, the first portion of cache memory and the LDS.

Abstract: A method and apparatus for integrating data compression in a computer system includes receiving first data at a first system level. Based upon a number of planes of the first data being less than or equal to a threshold, the data is compressed with a first data compression scheme, and transferred to a second system level for processing. Based upon the number of planes of the first data exceeding the threshold, the first data is transferred uncompressed to the second system level for processing. Based upon the received data at the second system level being compressed with the first compression scheme, the data is transferred to a third system level, and based upon the received data at the second system level being uncompressed with the first compression scheme, compressing the data with a second compression scheme, and transferring the compressed data to the third system level.

Abstract: An apparatus and method for efficiently supporting multiple peripheral communication protocols in a computing system. A computing system includes multiple servers with one or more of the servers using multiple connectors for connecting to multiple peripheral devices such as data storage devices. At least one of the connectors is able to support multiple communication protocols, rather than a single communication protocol. A processor of the server determines a peripheral device has been attached to a connector that supports multiple communication protocols, and the processor determines whether one of the multiple communication protocols supported by the particular connector matches the attached peripheral device's communication protocol. If so, the processor configures the connector with the matching communication protocol. Otherwise, the processor generates an indication that specifies that there is no match.

Abstract: A circuit design emulation system having a plurality of integrated circuits (ICs) includes a first IC. The first IC includes an originator circuit configured to issue a request of a transaction directed to a completer circuit. The request is specified in a communication protocol. The first IC includes a completer transactor circuit coupled to the originator circuit and configured to translate the request into request data. The first IC includes a first interface circuit configured to synchronize the request data from an originator clock domain to a transceiver clock domain operating at a higher frequency than the originator clock domain. The first IC includes a first transceiver circuit configured to convey the request data over a communication link that operates asynchronously to the originator clock domain.

Abstract: A computer-implemented method for resynchronization at execution time can include detecting, by at least one processor and during an execution time of an instruction, a resynchronization. The method can additionally include regenerating, by the at least one processor and in response to the detection, an instruction pointer. The method can also include performing, by the at least one processor and during the execution time of the instruction, the resynchronization by using the regenerated instruction pointer. Various other methods and systems are also disclosed.

Abstract: Graph analytics system are described. In accordance with the described techniques, a graph having vertices that include a first vertex and a second vertex that are associated with access control metadata are received. An updated graph is output based on a merging of the first vertex and the second vertex into a merged vertex of a group of vertices based on the first vertex and the second vertex being associated with access control metadata common to the first vertex and the second vertex and based on a reordering technique. A single copy of the access control metadata is stored for the first vertex and the second vertex.

Abstract: A method for cooling accelerators having back side power delivery components can include providing a printed circuit board having a first side that includes an integrated circuit and a first set of one or more power delivery components and a second side that is opposite the first side and that includes a second set of one or more power delivery components. The method can also include positioning a first cooling system to cool the integrated circuit and the first set of one or more power delivery components. The method can further include positioning a second cooling system to cool the second set of one or more power delivery components. Various other methods and systems are also disclosed.

Abstract: The disclosed computer-implemented method for video encoding rate control can include governing, by at least one processor, a video encoding rate at least partly in response to video encoding quality information. The method can additionally include generating, by the at least one processor, an encoded video data bitstream based on input pixel data and according to the video encoding rate. The method can also include determining, by the at least one processor, the video encoding quality information based on reconstructed pixel data. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: Devices and methods for rendering objects using ray tracing are provided which include generating a low resolution version of a high resolution mesh representing objects in the scene, determining points on curved surfaces of curved surface patches defined for one of triangles and bi-linear quadrangles of the low resolution version of the high resolution mesh, performing ray intersection testing by casting rays toward surfaces of the high resolution mesh which are approximated from new points calculated by offset values along interpolated normals from the points on the curved surfaces of the curved surface patches and rendering the objects in the scene based on the ray intersection testing.

Abstract: A disclosed technique includes based on a clock pattern, determining an enable configuration for setting enable signals for one or more multi-cycle paths of a hardware logic network; controlling a selector to set the enable configuration for the one or more multi-cycle paths; and executing testing operations for the hardware logic network with the one or more multi-cycle paths enabled according to the enable configuration.

Abstract: The disclosed computing device can include host circuitry configured to provide a physical function and guest circuitry configured to provide a virtual function. The host circuitry is configured to dynamically assign request identifiers for accessing at least the host circuitry in a manner that allows the request identifiers to change on a command-to-command basis instead of a time-to-time basis that uses fixed value request identifiers in time slices. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A computer-implemented method for dynamic resource management can include evaluating, by at least one processor, whether a priority of one or more processes associated with a request for one or more shared resources meets a threshold condition. The method can additionally include determining, by the at least one processor and in response to an evaluation that the priority meets the threshold condition, whether the one or more shared resources is available to meet the request. The method can further include completing, by the at least one processor and in response to a determination that the one or more shared resources is available, execution of the one or more processes. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A technique for generating video is provided. The technique includes obtaining a plurality of source frames with a wide-angle camera and a narrow-angle camera; identifying a plurality of central portions and a plurality of peripheral portions of the plurality of source frames based on image stabilization; and combining the plurality of central portions and the plurality of peripheral portions to generate a plurality of resulting frames of an output video.

Abstract: A computer-implemented method for data communication bus address sharing can include selecting, by at least one processor, one of two or more peripheral devices sharing an address of a data communication bus. The method can additionally include modulating, by the at least one processor, a duty cycle of a clock signal transmitted over the data communication bus to the two or more peripheral devices, wherein the modulating causes a low period of the clock signal to satisfy a threshold condition for indicating selection of the selected one of the two or more peripheral devices. The method can also include performing, by the at least one processor using the address, data communication over the data communication bus with the selected one of the two or more peripheral devices. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A method, apparatus and computer readable medium that use of a lightweight finite state machine (FSM) control flow block to enable limited execution of data-dependent control flow, thereby enhancing the control flow flexibility of array scale SIMD processors. In certain cases, the FSM block contains registers responsible for decoding and managing single global instructions into multiple local instructions that can incorporate data-dependent control flow.

Abstract: In response to receiving a scene description, a processing system generates a set of planes in the scene and a bounding volume representing a partition of the scene. Using the set of planes in the scene, a compute unit of an accelerated processing unit performs a spatial test on the bounding volume to determine whether the bounding volume intersects one or more planes of the set of planes in the scene. Based on the spatial test, the compute unit generates intersection data indicating whether the bounding volume intersects one or more planes of the set of planes in the scene. The accelerated processing unit then uses the intersection data to render the scene.

Abstract: An electronic device includes a processor that executes a guest operating system; a memory having a guest portion that is reserved for storing data and information to be accessed by the guest operating system; and an input-output memory management unit (IOMMU). The IOMMU writes, in the guest portion, information into guest buffers and/or logs used for communicating information from the IOMMU to the guest operating system. The IOMMU also reads, from the guest portion, information in guest buffers and/or logs used for communicating information from the guest operating system to the IOMMU.

Abstract: Performance adaptation for an integrated circuit includes receiving, by a workload prediction system of a hardware processor, telemetry data for one or more systems of the hardware processor. A workload prediction is determined by processing the telemetry data through a workload prediction model executed by a workload prediction controller of the workload prediction system. A profile is selected, from a plurality of profiles, that matches the workload prediction. The selected profile specifies one or more operating parameters for the hardware processor. The selected profile is provided to a power management controller of the hardware processor for controlling an operational characteristic of the one or more systems.