Abstract: A high-performance on-module caching architecture for hybrid memory modules is provided. A hybrid memory module includes a cache controller, a first volatile memory coupled to the cache controller, a first multiplexing data buffer coupled to the first volatile memory and the cache controller, and a first non-volatile memory coupled to the first multiplexing data buffer and the cache controller, wherein the first multiplexing data buffer multiplexes data between the first volatile memory and the first non-volatile memory and wherein the cache controller enables a tag checking operation to occur in parallel with a data movement operation. The hybrid memory module includes a volatile memory tag unit coupled to the cache controller, wherein the volatile memory tag unit includes a line connection that allows the cache controller to store a plurality of tags in the volatile memory tag unit and retrieve the plurality of tags from the volatile memory tag unit.

Abstract: A management node of a server maintains a database of configuration parameters that stores the individual configuration parameters for each compute node. In response to a boot request at a compute node, a configuration parameter control module at the node intercepts locally targeted requests to load configuration parameters. The configuration parameter module sends the requests to the management node and in response the management node sends configuration parameters responsive to the requests. The configuration parameter module provides the configuration parameters to the compute node, thereby emulating a local boot memory for the compute node.

Abstract: A master/slave configuration of a frequency locked Loop (FLL) decouples the process, target voltage, temperature (PVT) tracking goals of locking the loop from adapting the clock frequency in response to voltage droops in the supply. A master oscillator circuit receives a regulated supply voltage and supplies a master oscillator signal. A control circuit supplies a master frequency control signal to control a frequency of the master oscillator signal to a target frequency. A slave oscillator circuit is coupled to a regulated supply voltage and a droopy supply voltage and supplies a slave oscillator signal having a frequency responsive to a slave frequency control signal that is based on the master frequency control signal. The frequency of the second oscillator signal is further responsive to a voltage change of the droopy supply voltage.

Abstract: A memory manager of a processor identifies a block of data for eviction from a first memory module to a second memory module. In response, the processor copies only those portions of the data block that have been identified as modified portions to the second memory module. The amount of data to be copied is thereby reduced, improving memory management efficiency and reducing processor power consumption.

Abstract: A processing apparatus is provided that includes NVRAM and one or more processors configured to process a first set and a second set of instructions according to a hierarchical processing scope and process a scoped persistence barrier residing in the program after the first instruction set and before the second instruction set. The barrier includes an instruction to cause first data to persist in the NVRAM before second data persists in the NVRAM. The first data results from execution of each of the first set of instructions processed according to the one hierarchical processing scope. The second data results from execution of each of the second set of instructions processed according to the one hierarchical processing scope. The processing apparatus also includes a controller configured to cause the first data to persist in the NVRAM before the second data persists in the NVRAM based on the scoped persistence barrier.

Abstract: Techniques are provided herein for pre-emptively reinforcing one or more buses of a computing device against the effects of signal noise that could cause a reduction in signal integrity. The techniques generally include detecting an event (or “trigger”) that would tend to indicate that a reduction in signal integrity will occur, examining a reinforcement action policy and system status to determine what reinforcement action to take, and performing the reinforcement action.

Abstract: Systems, methods, and devices for determining a derived counter value based on a hardware performance counter. Example devices include input circuitry configured to input a hardware performance counter value; counter engine circuitry configured to determine the derived counter value by applying a model to the hardware performance counter value; and output circuitry configured to communicate the derived counter value to a consumer. In some examples, the consumer includes an operating system scheduler, a memory controller, a power manager, or a data prefetcher, or a cache controller. In some examples, the processor includes circuitry configured to dynamically change the model during operation of the processor. In some examples, the model includes or is generated by an artificial neural network (ANN).

Abstract: Improvements in graphics processing pipelines are disclosed. The graphics processing pipeline processes graphics objects in a particular order (application programming interface order—“API order”) as requested by an application or other entity. However, certain components within the graphics processing pipeline, such as the pixel shader stage, may process those objects out of order. A technique is provided herein to allow the pixel shader stage to complete and export processed fragments out of order. The technique includes using a scoreboard to determine whether fragments ready to be exported from a pixel shader stage are the newest fragments in API order. If the fragments are the newest in API order, then the fragments are exported. If the fragments are not the newest in API order, then the fragments are discarded.

Abstract: Techniques are provided for using a translation lookaside buffer to provide low latency memory address translations for data streams. Clients of a memory system first prepare the address translation cache hierarchy by requesting that a translation pre-fetch stream is initialized. After the translation pre-fetch stream is initialized, the cache hierarchy returns an acknowledgment of completion to the client, which then begins to access memory. Pre-fetch streams are specified in terms of address ranges and are performed for large contiguous portions of the virtual memory address space.

Abstract: Described is a method and system to efficiently compress and stream texture-space rendered content that enables low latency wireless virtual reality applications. In particular, camera motion, object motion/deformation, and shading information are decoupled and each type of information is then compressed as needed and streamed separately, while taking into account its tolerance to delays.

Abstract: Briefly, methods and apparatus to migrate a software thread from one wavefront executing on one execution unit to another wavefront executing on another execution unit whereby both execution units are associated with a compute unit of a processing device such as, for example, a GPU. The methods and apparatus may execute compiled dynamic thread migration swizzle buffer instructions that when executed allow access to a dynamic thread migration swizzle buffer that allows for the migration of register context information when migrating software threads. The register context information may be located in one or more locations of a register file prior to storing the register context information into the dynamic thread migration swizzle buffer. The method and apparatus may also return the register context information from the dynamic thread migration swizzle buffer to one or more different register file locations of the register file.

Abstract: A cooling system is provided for a 3D integrated circuit (IC) to deliver fluid in x, y, and z dimensions to interior regions of the IC as a means to regulate heat. An IC includes a microfluidic network of channels, at least one sensor and at least one microelectromechanical system (MEMS)-based device that is disposed within the network of channels and that is configured to regulate a flow of fluid within the network of channels. Each sensor monitors a state of the IC. Each MEMS-based device receives control signals based on a state of the IC and regulates a flow of fluid within the network of channels based on control signals that area received on a real-time basis based on changes detected in a state of the IC.

Abstract: A processing device is provided which includes a plurality of encoders each configured to compress a portion of data using a different compression algorithm. The processing device also includes one or more processors configured to cause an encoder, of the plurality of encoders, to compress the portion of data when it is determined that the portion of data, which is compressed by another encoder configured to compress the portion of data prior to the encoder in an encoder hierarchy, is not successfully compressed according to a compression metric by the other encoder in the encoder hierarchy. The one or more processors are also configured to prevent the encoder from compressing the portion of data when it is determined that the portion of data is successfully compressed according to the compression metric by the other encoder in the encoder hierarchy.

Abstract: Systems, apparatuses, and methods for dynamically optimizing memory traffic in multi-client systems are disclosed. A system includes a plurality of client devices, a memory subsystem, and a communication fabric coupled to the client devices and the memory subsystem. The system includes a first client which generates memory access requests targeting the memory subsystem. Prior to sending a given memory access request to the fabric, the first client analyzes metadata associated with data targeted by the given memory access request. If the metadata indicates the targeted data is the same as or is able to be derived from previously retrieved data, the first client prevents the request from being sent out on the fabric on the data path to memory subsystem. This helps to reduce memory bandwidth consumption and allows the fabric and the memory subsystem to stay in a low-power state for longer periods of time.

Abstract: A memory controller includes a host interface for receiving memory access requests including access addresses, a memory interface for providing memory accesses to a memory system, and an address decoder coupled to the host interface for programmably mapping the access addresses to selected ones of a plurality of regions. The address decoder is programmable to map the access addresses to a first region having a non-power-of-two size using a primary decoder and a secondary decoder each having power-of-two sizes, and providing a first region mapping signal in response. A command queue stores the memory access requests and region mapping signals. An arbiter picks the memory access requests from the command queue based on a plurality of criteria, which are evaluated based in part on the region mapping signals, and provides corresponding memory accesses to the memory interface in response.

Abstract: A non-uniform memory access system includes several nodes that each have one or more processors, caches, local main memory, and a local bus that connects a node's processor(s) to its memory. The nodes are coupled to one another over a collection of point-to-point interconnects, thereby permitting processors in one node to access data stored in another node. Memory access time for remote memory takes longer than local memory because remote memory accesses have to travel across a communications network to arrive at the requesting processor. In some embodiments, inter-cache and main-memory-to-cache latencies are measured to determine whether it would be more efficient to satisfy memory access requests using cached copies stored in caches of owning nodes or from main memory of home nodes.

Abstract: Systems, apparatuses, and methods for using a scoreboard to track updates to configuration state registers are disclosed. A system includes one or more processing nodes, one or more memory devices, a plurality of configuration state registers, and a communication fabric coupled to the processing unit(s) and memory device(s). The system uses a scoreboard to track updates to the configuration state registers during run-time. Prior to a node going into a power-gated state, the system stores only those configuration state registers that have changed. This reduces the amount of data written to memory on each transition into power-gated state, and increases the amount of time the node can spend in the power-gated state. Also, configuration state registers are grouped together to match the memory access granularity, and each group of configuration state registers has a corresponding scoreboard entry.

Abstract: In one form, an apparatus includes a memory controller. The memory controller includes a command queue and an arbiter. The command queue receives and stores memory access requests. The arbiter picks the memory access requests from the command queue based on a plurality of criteria, and provides picked memory access requests to a memory channel. The arbiter includes a streak counter for counting a number of consecutive memory access requests of a first type that the arbiter picks from the command queue. When the streak counter reaches a threshold, the arbiter suspends picking requests of the first type and picks at least one memory access request of a second type. The arbiter provides the at least one memory access request of the second type to the memory channel.

Abstract: An integrated circuit includes first and second through-silicon via (TSV) circuits and a steering logic circuit. The first TSV circuit has a first TSV and a first multiplexer for selecting between a first TSV data signal received from the first TSV and a first local data signal for transmission to a first TSV output terminal. The second TSV circuit includes a second TSV and a second multiplexer for selecting between a second TSV data signal received from the second TSV and the first local data signal for transmission to a second TSV output terminal. The steering logic circuit controls the first multiplexer to select the first local data signal and the second multiplexer to select the second TSV data signal in a first mode, and the first multiplexer to select the first TSV data signal and the second multiplexer to select the first local data signal in a second mode.

Abstract: A memory network includes a plurality of memory nodes each identifiable by an ordinal number m, and a set of links divided into N subsets of links, where each subset of links is identifiable by an ordinal number n. For each subset of the plurality of N subsets of links, each link in the subset connects two memory nodes that have ordinal numbers m differing by b(n-1), where b is a positive number. Each of the memory nodes is communicatively coupled to a processor via at least two non-overlapping pathways through the plurality of links.