Abstract: A technology capable of setting a leakage inductance to a predetermined value and enabling miniaturization is provided. In a transformer including a primary coil and a secondary coil which are coaxially provided, the primary coil includes a first primary coil portion and a second primary coil portion in series, the secondary coil includes a first secondary coil portion and a second secondary coil portion in series, the second primary coil portion and the second secondary coil portion are provided outside the first primary coil portion and the first secondary coil portion, and a degree of coupling between the second primary coil portion and the second secondary coil portion is set to be lower than a degree of coupling between the first primary coil portion and the first secondary coil portion.

Abstract: A technology capable of setting a leakage inductance to a predetermined value and enabling miniaturization is provided. In a transformer including a primary coil and a secondary coil which are coaxially provided, the primary coil includes a first primary coil portion and a second primary coil portion in series, the secondary coil includes a first secondary coil portion and a second secondary coil portion in series, the second primary coil portion and the second secondary coil portion are provided outside the first primary coil portion and the first secondary coil portion, and a degree of coupling between the second primary coil portion and the second secondary coil portion is set to be lower than a degree of coupling between the first primary coil portion and the first secondary coil portion.

Abstract: A protective system far a power transformer having a neutral line connected to ground where large currents can flow in the neutral line due to electro-magnetic disturbances. The system includes circuitry for: (a) sensing the current level in the neutral line and whether it exceeds a predetermined threshold for a predetermined period; and (b) sensing and processing the harmonic content of the load current and determining the existence of certain relationships of the “even” and “odd” harmonics. Signals, including alarms, indicative of excessive conditions are produced. The system may also include circuitry for sensing the load current level and generating a signal alarm if the load level is above a given value when the harmonics and the DC current have values in excess of certain predetermined values.

Abstract: The cooling system for a power transformer is activated by sensing and processing the frequency characteristic including the harmonic contents, of the inrush current into the transformer, when the transformer is first energized. The cooling system may include motors operating devices such as oil circulating pumps and fans causing a coolant to flow about the power transformer. The cooling system is deactivated by sensing when the transformer is de-energized and when its temperature is below a predetermined level.

Abstract: A system for cooling a power transformer which generates heat, when driving a load, includes cooling devices, such as fans and pumps, located about the transformer, which are powered for circulating a coolant about the transformer. Each cooling device has a motor which is energized in response to given temperature (heat) conditions. In systems embodying the invention, the currents flowing through the motors of cooling devices are sensed and monitored to determine whether the cooling devices are functioning correctly and to substitute functional cooling devices for those which are malfunctioning. Sensing the currents in the motors enables the early detection of fault conditions in the cooling system. It also enables the monitoring of operating conditions and running time of the cooling devices to aid in the maintenance and operation of the cooling system.

Abstract: A load tap changer (LTC) having a plurality of windings is coupled to one of the primary and secondary windings of a power transformer in order to regulate the output voltage of the power transformer. The LTC includes a plurality of taps physically and electrically connected to the LTC windings and the transformer's output voltage is increased/decreased by moving along the taps a contacting element whose movement is controlled by a rotating shaft driven by a motor. The tap being contacted is determined by sensing the direction and number of shaft rotations and by checking the number of shaft rotations specified to go from a tap to the next tap being contacted. The time for a full rotation of the shaft is also measured. Also, the temperature of the tanks containing the LTC taps and the power transformer is measured for each tap position.

Abstract: An improved Fast Recovery Diode comprises a main PN junction defining a central conduction region for conducting high current in a forward direction and a peripheral field spreading region surrounding the central conduction region for blocking high voltage in the reverse direction. The main PN junction has an avalanche voltage equal to or lower than an avalanche voltage of the peripheral field spreading region so substantially the entire said main PN junction participates in avalanche conduction. This rugged FRED structure can also be formed in MOSFETS, IGBTS and the like.

Abstract: Disclosed are a variety of junction termination structures for high voltage semiconductor power devices. The structures are specifically aimed at providing a high breakdown voltage while being constructed with a minimal number of process steps. The combination of an RIE etch and/or implantation and anneal process with a finely patterned mesh provides the desired radial gradient for maximum breakdown voltage. The structures provide control of both the conductivity and charge density within the region. These structures can beneficially be applied to all high voltage semiconductor device structures, but are of particular interest for wide bandgap devices as they tend to have very high breakdown fields and scaled dimensions of the depletion layer width.

Abstract: A SiC die with Os and/or W/WC/TiC contacts and metal conductors is encapsulated either alone or on a ceramic substrate using a borosilicate (BSG) glass that is formed at a temperature well below upper device operating temperature limits but serves as a stable protective layer above the operating temperature (over 1000° C., preferably >1200° C.). The glass is preferably 30-50% B2O3/70-50% SiO2, formed by reacting a mixed powder, slurry or paste of the components at 460°-1000° C. preferably about 700° C. The die can be mounted on the ceramic substrate using the BSG as an adhesive. Metal conductors on the ceramic substrate are also protected by the BSG. The preferred ceramic substrate is AlN but SiC/AlN or Al2 03 can be used.

Abstract: The invention involves a method of packaging and interconnecting four power transistor dies to operate at a first frequency without oscillation at a second frequency higher than the first frequency but lower than a cutoff frequency of the transistors. The dies are mounted on a substrate with a lower side (drain) of each die electrically and thermally bonded to a first area of a conductive layer on the substrate. A source of each die is electrically connected to a second area of the conductive layer on the substrate. A gate of each die is electrically connected to a third, common interior central area of the conductive layer on the substrate via separate electrical leads.

Abstract: The invention involves a method of packaging and interconnecting four power transistor dies to operate at a first frequency without oscillation at a second frequency higher than the first frequency but lower than a cutoff frequency of the transistors. The method comprises mounting the dies on a substrate with a lower side (drain) of each die electrically and thermally bonded to a first area of a conductive layer on the substrate; electrically connecting a source of each die to a second area of the conductive layer on the substrate; and electrically connecting a gate of each die to a third, common interior central area of the conductive layer on the substrate via separate electrical leads.

Abstract: A SiC die with Os and/or W/WC/TiC contacts and metal conductors is encapsulated either alone or on a ceramic substrate using a borosilicate (BSG) glass that is formed at a temperature well below upper device operating temperature limits but serves as a stable protective layer above the operating temperature (over 1000° C., preferably >1200° C.). The glass is preferably 30-50% B2O3/70-50% SiO2, formed by reacting a mixed powder, slurry or paste of the components at 460°-1000° C. preferably about 700° C. The die can be mounted on the ceramic substrate using the BSG as an adhesive. Metal conductors on the ceramic substrate are also protected by the BSG. The preferred ceramic substrate is AlN but SiC/AlN or Al2O3 can be used.

Abstract: The disclosure relates to a plasma etch chemistry which allows a near perfectly anisotropic etch of silicon. A Cl-based plasma etch such as SiCl4+Cl2 has CH2Br2 added thereto, readily allowing the anisotropic etching of silicon. The silicon surface facing the discharge is subjected to ion bombardment, allowing the volatilization (etching) of silicon as a Si—Cl—Br compound. The Br which adsorbs on the sidewalls of the etched silicon passivates them from the etching. This new plasma etch chemistry yields a very smooth etched surface, and the etch rate is relatively insensitive to the electrical conductivity of the silicon. The use of dibromomethane is an improvement over the prior art which typically used HBr; a poisonous and ozone depleting gas. Dibromomethane is a relatively safe gas and not ozone depleting, yet giving substantially similar results in plasma etching of silicon, silicon nitride, and other materials.

Abstract: An improved Fast Recovery Diode comprises a main PN junction defining a central conduction region for conducting high current in a forward direction and a peripheral field spreading region surrounding the central conduction region for blocking high voltage in the reverse direction. The main PN junction has an avalanche voltage equal to or lower than an avalanche voltage of the peripheral field spreading region so substantially the entire said main PN junction participates in avalanche conduction. This rugged FRED structure can also be formed in MOSFETS, IGBTS and the like.

Abstract: A power MOSFET type device, which can include an IGBT or other VDMOS device having similar forward transfer characteristics, is formed with an asymmetrical channel, to produce different gate threshold voltage characteristics in different parts of the device. The different gate threshold voltage characteristics can be achieved either by different source region doping concentrations or different body region doping concentrations subjacent the gate oxide, or by asymmetrical gate oxide thicknesses. The portion of overall channel affected can be 50% or such other proportion as the designer chooses, to reduce the zero temperature coefficient point of the device and improve its Safe Operating Area in linear operation, while retaining low conduction loss. Multiple power MOSFET devices with asymmetrical channels can easily be used safely in parallel linear power amplifier circuits.

Abstract: A power MOSFET type device, which can include an IGBT or other VDMOS device having similar forward transfer characteristics, is formed with an asymmetrical channel, to produce different gate threshold voltage characteristics in different parts of the device. The different gate threshold voltage characteristics can be achieved either by different source region doping concentrations or different body region doping concentrations subjacent the gate oxide, or by asymmetrical gate oxide thicknesses. The portion of overall channel affected can be 50% or such other proportion as the designer chooses, to reduce the zero temperature coefficient point of the device and improve its Safe Operating Area in linear operation, while retaining low conduction loss. Multiple power MOSFET devices with asymmetrical channels can easily be used safely in parallel linear power amplifier circuits.

Abstract: A power MOSFET type device, which can include an IGBT or other VDMOS device having similar forward transfer characteristics, is formed with an asymmetrical channel, to produce different gate threshold voltage characteristics in different parts of the device. The different gate threshold voltage characteristics can be achieved either by different source region doping concentrations or different body region doping concentrations subjacent the gate oxide, or by asymmetrical gate oxide thicknesses. The portion of overall channel affected can be 50% or such other proportion as the designer chooses, to reduce the zero temperature coefficient point of the device and improve its Safe Operating Area in linear operation, while retaining low conduction loss. Multiple power MOSFET devices with asymmetrical channels can easily be used safely in parallel linear power amplifier circuits.

Abstract: A power MOSFET type device, which can include an IGBT or other VDMOS device having similar forward transfer characteristics, is formed with an asymmetrical channel, to produce different gate threshold voltage characteristics in different parts of the device. The different gate threshold voltage characteristics can be achieved either by different source region doping concentrations or different body region doping concentrations subjacent the gate oxide, or by asymmetrical gate oxide thicknesses. The portion of overall channel affected can be 50% or such other proportion as the designer chooses, to reduce the zero temperature coefficient point of the device and improve its Safe Operating Area in linear operation, while retaining low conduction loss. Multiple power MOSFET devices with asymmetrical channels can easily be used safely in parallel linear power amplifier circuits.

Abstract: A display system for translucent objects comprising a shelf having an upper surface and a lower surface with apertures extending through the shelf. A fiber optic strand has an input end and an output end positioned through each aperture with its output end located at the upper surface of a shelf and with the strands extending downwardly to the bottom end and rearwardly thereof and terminating at a remote location. A source of illumination is located adjacent to the input end with a color wheel is rotatable in a path of travel between the source of illumination and the input ends of the bundle, the color wheel including segments of different colors whereby rotation of the color wheel while the source of illumination is illuminated will effect a continuous change of colors at the output end for providing a simulated internal luminescence of the objects being displayed. A supplemental shelf is located above the shelf with a lower surface.

Abstract: A recessed gate power MOSFET is formed on a substrate (20) including a P-body layer (26), N-drain layer (24) and optional P+ layer (22) for IGBT. A trenching protective layer (30) formed on the substrate upper surface (28) is patterned to define exposed areas (46) as stripes or a matrix, and protected areas. Sidewall spacers (44) of predetermined thickness (52) with inner surfaces (48) contact the protective layer sidewalls. A first trench (50) is formed in substrate areas (46) with sidewalls aligned to the sidewall spacer outer surfaces (47) and extending depthwise through the P-body layer (26) to at least a predetermined depth (56). Gate oxide (60) is formed on the trench walls and gate polysilicon (62) refills the trench to a level (64) near substrate upper surface (28). Oxide (68) between sidewall spacers (44) covers polysilicon (62). Removing the protective layer exposes upper substrate surface (28') between spacer inner surfaces (48).