Abstract: A technology capable of setting a leakage inductance to a predetermined value and enabling miniaturization is provided. In a transformer including a primary coil and a secondary coil which are coaxially provided, the primary coil includes a first primary coil portion and a second primary coil portion in series, the secondary coil includes a first secondary coil portion and a second secondary coil portion in series, the second primary coil portion and the second secondary coil portion are provided outside the first primary coil portion and the first secondary coil portion, and a degree of coupling between the second primary coil portion and the second secondary coil portion is set to be lower than a degree of coupling between the first primary coil portion and the first secondary coil portion.

Abstract: A technology capable of setting a leakage inductance to a predetermined value and enabling miniaturization is provided. In a transformer including a primary coil and a secondary coil which are coaxially provided, the primary coil includes a first primary coil portion and a second primary coil portion in series, the secondary coil includes a first secondary coil portion and a second secondary coil portion in series, the second primary coil portion and the second secondary coil portion are provided outside the first primary coil portion and the first secondary coil portion, and a degree of coupling between the second primary coil portion and the second secondary coil portion is set to be lower than a degree of coupling between the first primary coil portion and the first secondary coil portion.

Abstract: An improved Fast Recovery Diode comprises a main PN junction defining a central conduction region for conducting high current in a forward direction and a peripheral field spreading region surrounding the central conduction region for blocking high voltage in the reverse direction. The main PN junction has an avalanche voltage equal to or lower than an avalanche voltage of the peripheral field spreading region so substantially the entire said main PN junction participates in avalanche conduction. This rugged FRED structure can also be formed in MOSFETS, IGBTS and the like.

Abstract: Disclosed are a variety of junction termination structures for high voltage semiconductor power devices. The structures are specifically aimed at providing a high breakdown voltage while being constructed with a minimal number of process steps. The combination of an RIE etch and/or implantation and anneal process with a finely patterned mesh provides the desired radial gradient for maximum breakdown voltage. The structures provide control of both the conductivity and charge density within the region. These structures can beneficially be applied to all high voltage semiconductor device structures, but are of particular interest for wide bandgap devices as they tend to have very high breakdown fields and scaled dimensions of the depletion layer width.

Abstract: A SiC die with Os and/or W/WC/TiC contacts and metal conductors is encapsulated either alone or on a ceramic substrate using a borosilicate (BSG) glass that is formed at a temperature well below upper device operating temperature limits but serves as a stable protective layer above the operating temperature (over 1000° C., preferably >1200° C.). The glass is preferably 30-50% B2O3/70-50% SiO2, formed by reacting a mixed powder, slurry or paste of the components at 460°-1000° C. preferably about 700° C. The die can be mounted on the ceramic substrate using the BSG as an adhesive. Metal conductors on the ceramic substrate are also protected by the BSG. The preferred ceramic substrate is AlN but SiC/AlN or Al2 03 can be used.

Abstract: The invention involves a method of packaging and interconnecting four power transistor dies to operate at a first frequency without oscillation at a second frequency higher than the first frequency but lower than a cutoff frequency of the transistors. The dies are mounted on a substrate with a lower side (drain) of each die electrically and thermally bonded to a first area of a conductive layer on the substrate. A source of each die is electrically connected to a second area of the conductive layer on the substrate. A gate of each die is electrically connected to a third, common interior central area of the conductive layer on the substrate via separate electrical leads.

Abstract: The invention involves a method of packaging and interconnecting four power transistor dies to operate at a first frequency without oscillation at a second frequency higher than the first frequency but lower than a cutoff frequency of the transistors. The method comprises mounting the dies on a substrate with a lower side (drain) of each die electrically and thermally bonded to a first area of a conductive layer on the substrate; electrically connecting a source of each die to a second area of the conductive layer on the substrate; and electrically connecting a gate of each die to a third, common interior central area of the conductive layer on the substrate via separate electrical leads.

Abstract: A SiC die with Os and/or W/WC/TiC contacts and metal conductors is encapsulated either alone or on a ceramic substrate using a borosilicate (BSG) glass that is formed at a temperature well below upper device operating temperature limits but serves as a stable protective layer above the operating temperature (over 1000° C., preferably >1200° C.). The glass is preferably 30-50% B2O3/70-50% SiO2, formed by reacting a mixed powder, slurry or paste of the components at 460°-1000° C. preferably about 700° C. The die can be mounted on the ceramic substrate using the BSG as an adhesive. Metal conductors on the ceramic substrate are also protected by the BSG. The preferred ceramic substrate is AlN but SiC/AlN or Al2O3 can be used.

Abstract: The disclosure relates to a plasma etch chemistry which allows a near perfectly anisotropic etch of silicon. A Cl-based plasma etch such as SiCl4+Cl2 has CH2Br2 added thereto, readily allowing the anisotropic etching of silicon. The silicon surface facing the discharge is subjected to ion bombardment, allowing the volatilization (etching) of silicon as a Si—Cl—Br compound. The Br which adsorbs on the sidewalls of the etched silicon passivates them from the etching. This new plasma etch chemistry yields a very smooth etched surface, and the etch rate is relatively insensitive to the electrical conductivity of the silicon. The use of dibromomethane is an improvement over the prior art which typically used HBr; a poisonous and ozone depleting gas. Dibromomethane is a relatively safe gas and not ozone depleting, yet giving substantially similar results in plasma etching of silicon, silicon nitride, and other materials.

Abstract: An improved Fast Recovery Diode comprises a main PN junction defining a central conduction region for conducting high current in a forward direction and a peripheral field spreading region surrounding the central conduction region for blocking high voltage in the reverse direction. The main PN junction has an avalanche voltage equal to or lower than an avalanche voltage of the peripheral field spreading region so substantially the entire said main PN junction participates in avalanche conduction. This rugged FRED structure can also be formed in MOSFETS, IGBTS and the like.

Abstract: The invention proposes a single stage, single switch, input-output isolated converter configuration using a hybrid combination of forward and flyback converters. The converter operates at a high input power factor with a regulated DC output voltage. It makes use of a novel control scheme utilizing duty cycle control at two discrete operating frequencies. Although the invention employs two frequencies, it does not use a continuous frequency variation. The proposed configuration has the advantage of reduced peak current stresses on the components and is specifically suited for ‘buck’ applications where low DC output voltages (e.g. 24V, 48V) are needed. The proposed configuration will be of specific interest to industries associated with battery charging and uninterruptible power supply (UPS) systems.

Abstract: A power MOSFET type device, which can include an IGBT or other VDMOS device having similar forward transfer characteristics, is formed with an asymmetrical channel, to produce different gate threshold voltage characteristics in different parts of the device. The different gate threshold voltage characteristics can be achieved either by different source region doping concentrations or different body region doping concentrations subjacent the gate oxide, or by asymmetrical gate oxide thicknesses. The portion of overall channel affected can be 50% or such other proportion as the designer chooses, to reduce the zero temperature coefficient point of the device and improve its Safe Operating Area in linear operation, while retaining low conduction loss. Multiple power MOSFET devices with asymmetrical channels can easily be used safely in parallel linear power amplifier circuits.

Abstract: The invention involves a method of packaging and interconnecting four power transistor dies to operate at a first frequency without oscillation at a second frequency higher than the first frequency but lower than a cutoff frequency of the transistors. The method comprises mounting the dies on a substrate with a lower side (drain) of each die electrically and thermally bonded to a first area of a conductive layer on the substrate; electrically connecting a source of each die to a second area of the conductive layer on the substrate; and electrically connecting a gate of each die to a third, common interior central area of the conductive layer on the substrate via separate electrical leads.

Abstract: A power MOSFET type device, which can include an IGBT or other VDMOS device having similar forward transfer characteristics, is formed with an asymmetrical channel, to produce different gate threshold voltage characteristics in different parts of the device. The different gate threshold voltage characteristics can be achieved either by different source region doping concentrations or different body region doping concentrations subjacent the gate oxide, or by asymmetrical gate oxide thicknesses. The portion of overall channel affected can be 50% or such other proportion as the designer chooses, to reduce the zero temperature coefficient point of the device and improve its Safe Operating Area in linear operation, while retaining low conduction loss. Multiple power MOSFET devices with asymmetrical channels can easily be used safely in parallel linear power amplifier circuits.

Abstract: A power MOSFET type device, which can include an IGBT or other VDMOS device having similar forward transfer characteristics, is formed with an asymmetrical channel, to produce different gate threshold voltage characteristics in different parts of the device. The different gate threshold voltage characteristics can be achieved either by different source region doping concentrations or different body region doping concentrations subjacent the gate oxide, or by asymmetrical gate oxide thicknesses. The portion of overall channel affected can be 50% or such other proportion as the designer chooses, to reduce the zero temperature coefficient point of the device and improve its Safe Operating Area in linear operation, while retaining low conduction loss. Multiple power MOSFET devices with asymmetrical channels can easily be used safely in parallel linear power amplifier circuits.

Abstract: A power MOSFET transistor is formed on a substrate including a source, body layer, and drain layer and an optional fourth layer for an IGBT. The device is characterized by a conductive gate having a high conductivity metal layer coextensive with a polysilicon layer for high power and high speed operation.

Abstract: A power MOSFET type device, which can include an IGBT or other VDMOS device having similar forward transfer characteristics, is formed with an asymmetrical channel, to produce different gate threshold voltage characteristics in different parts of the device. The different gate threshold voltage characteristics can be achieved either by different source region doping concentrations or different body region doping concentrations subjacent the gate oxide, or by asymmetrical gate oxide thicknesses. The portion of overall channel affected can be 50% or such other proportion as the designer chooses, to reduce the zero temperature coefficient point of the device and improve its Safe Operating Area in linear operation, while retaining low conduction loss. Multiple power MOSFET devices with asymmetrical channels can easily be used safely in parallel linear power amplifier circuits.

Abstract: A recessed gate power MOSFET is formed on a substrate (20) including a P-body layer (26), N-drain layer (24) and optional P+ layer (22) for IGBT. A trenching protective layer (30) formed on the substrate upper surface (28) is patterned to define exposed areas (46) as stripes or a matrix, and protected areas. Sidewall spacers (44) of predetermined thickness (52) with inner surfaces (48) contact the protective layer sidewalls. A first trench (50) is formed in substrate areas (46) with sidewalls aligned to the sidewall spacer outer surfaces (47) and extending depthwise through the P-body layer (26) to at least a predetermined depth (56). Gate oxide (60) is formed on the trench walls and gate polysilicon (62) refills the trench to a level (64) near substrate upper surface (28). Oxide (68) between sidewall spacers (44) covers polysilicon (62). Removing the protective layer exposes upper substrate surface (28') between spacer inner surfaces (48).

Abstract: A gate power MOSFET on substrate (20) has a P-body layer (26), N-drain layer (24) and optional P+ layer (22) for IGBT. Layer (430) on surface (28) patterns areas (446) as stripes or a matrix, and protected areas. Undercut sidewalls (444) of thickness (452), with protruding rims (447), contact the sides of layer (434'). Trench (450) in areas (446) has silicon sidewalls aligned to oxide sidewall (447) and extending depthwise through P-body layer (26) to depth (456). Gate oxide (460) is formed on the trench walls and gate polysilicon (462) refills trench (450) to a level (464) near surface (28) demarcated by the undercut sidewall rims (447). Oxide (468) between spacers (444) covers polysilicon (462). Removing layer (430) exposes surface (28') between the sidewalls (444). Source layer (72) is doped atop the body layer (26') and then trenched to form trench (80) having sidewalls aligned to inner side faces of sidewalls (444).

Abstract: For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (.about.10.sup.14 /cm.sup.3) to block reverse bias voltage. The N+ layer is >20 .mu.m thick and doped below .about.10.sup.17 /cm.sup.3 but above the N- doping to enhance output impedance and reduce gain at high V.sub.ce conditions. Or the N+ layer is formed with a thin (.about.5 .mu.m) highly doped (>10.sup.17 /cm.sup.3) layer and a thick (>20 .mu.m) layer of .about.10.sup.16 /cm.sup.3 doping. A platinum dose of 10.sup.13 to 10.sup.16 /cm.sup.3 is ion implanted and diffused into the silicon to effect lifetime control. Gate and source contacts and body and source diffusions have an inter-digitated finger pattern with complementary tapers to minimize current crowding and wide gate buses to minimize signal delay.