Abstract: A power MOSFET transistor is formed on a substrate including a source, body layer, and drain layer and an optional fourth layer for an IGBT. The device is characterized by a conductive gate having a high conductivity metal layer coextensive with a polysilicon layer for high power and high speed operation.

Abstract: A power MOSFET type device, which can include an IGBT or other VDMOS device having similar forward transfer characteristics, is formed with an asymmetrical channel, to produce different gate threshold voltage characteristics in different parts of the device. The different gate threshold voltage characteristics can be achieved either by different source region doping concentrations or different body region doping concentrations subjacent the gate oxide, or by asymmetrical gate oxide thicknesses. The portion of overall channel affected can be 50% or such other proportion as the designer chooses, to reduce the zero temperature coefficient point of the device and improve its Safe Operating Area in linear operation, while retaining low conduction loss. Multiple power MOSFET devices with asymmetrical channels can easily be used safely in parallel linear power amplifier circuits.

Abstract: A display system for translucent objects comprising a shelf having an upper surface and a lower surface with apertures extending through the shelf. A fiber optic strand has an input end and an output end positioned through each aperture with its output end located at the upper surface of a shelf and with the strands extending downwardly to the bottom end and rearwardly thereof and terminating at a remote location. A source of illumination is located adjacent to the input end with a color wheel is rotatable in a path of travel between the source of illumination and the input ends of the bundle, the color wheel including segments of different colors whereby rotation of the color wheel while the source of illumination is illuminated will effect a continuous change of colors at the output end for providing a simulated internal luminescence of the objects being displayed. A supplemental shelf is located above the shelf with a lower surface.

Abstract: A recessed gate power MOSFET is formed on a substrate (20) including a P-body layer (26), N-drain layer (24) and optional P+ layer (22) for IGBT. A trenching protective layer (30) formed on the substrate upper surface (28) is patterned to define exposed areas (46) as stripes or a matrix, and protected areas. Sidewall spacers (44) of predetermined thickness (52) with inner surfaces (48) contact the protective layer sidewalls. A first trench (50) is formed in substrate areas (46) with sidewalls aligned to the sidewall spacer outer surfaces (47) and extending depthwise through the P-body layer (26) to at least a predetermined depth (56). Gate oxide (60) is formed on the trench walls and gate polysilicon (62) refills the trench to a level (64) near substrate upper surface (28). Oxide (68) between sidewall spacers (44) covers polysilicon (62). Removing the protective layer exposes upper substrate surface (28') between spacer inner surfaces (48).

Abstract: A gate power MOSFET on substrate (20) has a P-body layer (26), N-drain layer (24) and optional P+ layer (22) for IGBT. Layer (430) on surface (28) patterns areas (446) as stripes or a matrix, and protected areas. Undercut sidewalls (444) of thickness (452), with protruding rims (447), contact the sides of layer (434'). Trench (450) in areas (446) has silicon sidewalls aligned to oxide sidewall (447) and extending depthwise through P-body layer (26) to depth (456). Gate oxide (460) is formed on the trench walls and gate polysilicon (462) refills trench (450) to a level (464) near surface (28) demarcated by the undercut sidewall rims (447). Oxide (468) between spacers (444) covers polysilicon (462). Removing layer (430) exposes surface (28') between the sidewalls (444). Source layer (72) is doped atop the body layer (26') and then trenched to form trench (80) having sidewalls aligned to inner side faces of sidewalls (444).

Abstract: For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (.about.10.sup.14 /cm.sup.3) to block reverse bias voltage. The N+ layer is >20 .mu.m thick and doped below .about.10.sup.17 /cm.sup.3 but above the N- doping to enhance output impedance and reduce gain at high V.sub.ce conditions. Or the N+ layer is formed with a thin (.about.5 .mu.m) highly doped (>10.sup.17 /cm.sup.3) layer and a thick (>20 .mu.m) layer of .about.10.sup.16 /cm.sup.3 doping. A platinum dose of 10.sup.13 to 10.sup.16 /cm.sup.3 is ion implanted and diffused into the silicon to effect lifetime control. Gate and source contacts and body and source diffusions have an inter-digitated finger pattern with complementary tapers to minimize current crowding and wide gate buses to minimize signal delay.

Abstract: A continuously variable transmission includes a pump (258) driven by an input shaft (256) against a wedge-shaped swashplate (260). Hydraulic fluid pressurized in the pump flows through ports (402) in a pump cylinder block (422) into kidney-shaped slots (406) in the swashplate (260), and from there flows into and pressurizes a series of cylinders (394) in a motor cylinder block (366). The pump and motor exert first and second components of torque on a swashplate (260) in the rotational direction on the input shaft (256), and the hydraulic system pressure in the swashplate slots exerts a third component of torque in the same direction on the swashplate (260). The third torque component is a product of the hydraulic system pressure and the differential area of the two ends of the high pressure slot (406P) at the narrow and thick sides of the wedge-shaped swashplate (260).

Abstract: For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (.about.10.sup.14 /cm.sup.3) to block reverse bias voltage. The N+ layer is >20 .mu.m thick and doped below .about.10.sup.17 /cm.sup.3 but above the N- doping to enhance output impedance and reduce gain at high V.sub.ce conditions. Or the N+ layer is formed with a thin (.about.5 .mu.m) highly doped (>10.sup.17 /cm.sup.3) layer and a thick (>20 .mu.m) layer of .about.10.sup.16 /cm.sup.3 doping. A platinum dose of 10.sup.13 to 10.sup.16 /cm.sup.2 is ion implanted and diffused into the silicon to effect lifetime control. Gate and source contacts and body and source diffusions have an inter-digitated finger pattern with complementary tapers to minimize current crowding and wide gate buses to minimize signal delay.

Abstract: A recessed gate power MOSFET is formed on a substrate (20) including a P-body layer (26), N-drain layer (24) and optional P+ layer (22) for IGBT. A trenching protective layer (30) formed on the substrate upper surface (28) is patterned to define exposed areas (46) as stripes or a matrix, and protected areas. Sidewall spacers (44) of predetermined thickness (52) with inner surfaces (48) contact the protective layer sidewalls. A first trench (50) is formed in substrate areas (46) with sidewalls aligned to the sidewall spacer outer surfaces (47) and extending depthwise through the P-body layer (26) to at least a predetermined depth (56). Gate oxide (60) is formed on the trench walls and gate polysilicon (62) refills the trench to a level (64) near substrate upper surface (28). Oxide (68) between sidewall spacers (44) covers polysilicon (62). Removing the protective layer exposes upper substrate surface (28') between spacer inner surfaces (48).

Abstract: For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (.about.10.sup.14 /cm.sup.3) to block reverse bias voltage. The N+ layer is >20 .mu.m thick and doped below .about.10.sup.17 /cm.sup.3 but above the N- doping to enhance output impedance and reduce gain at high V.sub.ce conditions. Or the N+ layer is formed with a thin (.about.5 .mu.m) highly doped (>10.sup.17 /cm.sup.3) layer and a thick (>20 .mu.m) layer of .about.10.sup.16 /cm.sup.3 doping. A platinum dose of 10.sup.13 to .about.10.sup.16 /cm.sup.2 is ion implanted and diffused into the silicon to effect lifetime control. Gate and source contacts and body and source diffusions have an inter-digitated finger pattern with complementary tapers to minimize current crowding and wide gate buses to minimize signal delay.

Abstract: A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative junctions within a silicon substrate and the conductive structures formed atop the substrate. A trench is formed in the upper silicon surface and a source conductive layer is deposited to electrically contact the source region as a gate conductive layer is deposited atop the gate oxide layer. The trench sidewall is profile tailored using a novel O.sub.2 -SF.sub.6 plasma etch technique. An oxide sidewall spacer is formed on the sides of the pattern definer and gate oxide structures, before depositing the conductive material. A planarizing layer is applied and used as a mask for selectively removing any conductive material deposited atop the oxide spacer.

Abstract: A stationary battery testing device as provided for measuring imminent battery failure while the battery is in a float mode. The device includes a circuitry for measuring the internal resistance changes of a battery and then comparing them over a predetermined duration of time so as to provide audible or visual discernable signals to indicate an imminent battery failure after the expiration of said predetermined period of time. An additional temperature monitoring component may be provided for the device to monitor internal changes within the battery with respect to temperature. This can also be combined in a temperature compensated automatic adjustment of voltage and alarm thresholds in an active feedback loop to augment and broaden the basis of stationary battery applications where the battery testing device can be used.

Abstract: A field-effect, power-MOS transistor wherein a region under the gate contact pad is specially doped with a dopant that is electrically compatible with that in the transistor's channel to obviate problems of electrical breakdown in that region.

Abstract: For IGBT, MCT or like devices, the substrate is formed with P+, N+ and N- layers and PN diffusions to define body and source regions in the N-layer and a MOS-gated channel at the upper surface. The N-layer is sized and doped (.about.10.sup.14 /cm.sup.3) to block reverse bias voltage. The N+ layer is >20 .mu.m thick and doped below .about.10.sup.17 /cm.sup.3 but above the N- doping to enhance output impedance and reduce gain at high V.sub.ce conditions. Or the N+ layer is formed with a thin (.about.5 .mu.m) highly doped (>10.sup.17 /cm.sup.3) layer and a thick (>20 .mu.m) layer of .about.10.sup.16 /cm.sup.3 doping. A platinum dose of 10.sup.13 to 10.sup.16 /cm.sup.2 is ion implanted and diffused into the silicon to effect lifetime control. Gate and source contacts and body and source diffusions have an inter-digitated finger pattern with complementary tapers to minimize current crowding and wide gate buses to minimize signal delay.

Abstract: A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative junctions within a silicon substrate and the conductive structures formed atop the substrate. A trench is formed in the upper silicon surface and a source conductive layer is deposited to electrically contact the source region as a gate conductive layer is deposited atop the gate oxide layer. The trench sidewall is profile tailored using a novel O.sub.2 -SF.sub.6 plasma etch technique. An oxide sidewall spacer is formed on the sides of the pattern definer and gate oxide structures, before depositing the conductive material. A planarizing layer is applied and used as a mask for selectively removing any conductive material deposited atop the oxide spacer.

Abstract: A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative junctions within a silicon substrate and the conductive structure formed atop the substrate. A trench is formed in the upper silicon surface and a source conductive layer is deposited to electrically contact the source region as a gate conductive layer is deposited atop the gate oxide layer. The trench sidewall is profile tailored using a novel O.sub.2 -SF.sub.6 plasma etch technique. An oxide sidewall spacer is formed on the sides of the pattern definer and gate oxide structures, before depositing the conductive material. A planarizing layer is applied and used as a mask for selectively removing any conductive material deposited atop the oxide spacer.

Abstract: A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative junctions within a silicon substrate and the conductive structures formed atop the substrate. A trench is formed in the upper silicon surface and a source conductive layer is deposited to electrically contact the source region as a gate conductive layer is deposited atop the gate oxide layer. The trench sidewall is profile tailored using a novel O.sub.2 -SF.sub.6 plasma etch technique. An oxide sidewall spacer is formed on the sides of the pattern definer and gate oxide structures, before depositing the conductive material. A planarizing layer is applied and used as a mask for selectively removing any conductive material deposited atop the oxide spacer.

Abstract: A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative junctions within a silicon substrate and the conductive structures formed atop the substrate. A trench is formed in the upper silicon surface and a source conductive layer is deposited to electrically contact the source region as a gate conductive layer is deposited atop the gate oxide layer. The trench sidewall is profile tailored using a novel O.sub.2 -SF.sub.6 plasma etch technique. An oxide sidewall spacer is formed on the sides of the pattern definer and gate oxide structure, before depositing the conductive material. A planarizing layer is applied and used as a mask for selectively removing any conductive material deposited atop the oxide spacer.

Abstract: A dopant-opaque layer of polysilicon is deposited on gate oxide on the upper substrate surface to serve as a pattern definer during fabrication of the device. It provides control over successive P and N doping steps used to create the necessary operative junctions within a silicon substrate and the conductive structures formed atop the substrate. A trench is formed in the upper silicon surface and a source conductive layer is deposited to electrically contact the source region as a gate conductive layer is deposited atop the gate oxide layer. The trench sidewall is profile tailored using a novel O.sub.2 --SF.sub.6 plasma etch technique. An oxide sidewall spacer is formed on the sides of the pattern definer and gate oxide structures, before depositing the conductive material. A planarizing layer is applied and used as a mask for selectively removing any conductive material deposited atop the oxide spacer.

Abstract: A mask-defect-immune process for making MOS semiconductor devices. The process features the creation of a surrogate mask in semiconductor wafer material per se, thus to eliminate the requirement that plural masks be used, and that plural mask alignments be performed. In all ways of practicing the invention, a surrogate mask is created in a dopant protective region.