Abstract: A test carrier carried in a state of accommodating a device under test (DUT) includes: a carrier body that holds the DUT; and a lid member that covers the DUT and is attached to the carrier body. The lid member includes: a plate-like main body; and a pusher protruding from the main body in a convex shape.

Abstract: Efficient and effective testing systems and methods are presented. In one embodiment, a testing system includes: a user interface configured to enable user interaction with the system; a test board configured to communicatively couple with a plurality of devices under test (DUTs), wherein the DUTs are compute express link (CXL) protocol compliant; and a tester configured to direct testing of the plurality of DUTs, wherein the tester manages testing of the plurality of DUTs, including managing CXL protocol aspects of the testing. In one exemplary implementation, the tester prevents testing of a first one of the plurality of DUTs from detrimentally interfering with testing of a second one of the plurality of DUTs.

Abstract: Efficient and effective testing systems and methods are presented. In one embodiment, a system includes: a user interface configured to enable user interaction with the system; a test board configured to communicatively couple with a plurality of devices under test (DUTs), wherein the DUTs are compute express link (CXL) protocol compliant; and a tester configured to direct testing of the plurality of DUTs, wherein the tester is configured to enable hot add of one of the plurality of DUTs without interfering with testing of the other DUTS. In one exemplary implementation, the DUTs are memory devices and the DUTs can operate as extended memory. An added DUT can be automatically recognized by a host in a way that is transparent to users (e.g., BIOS can direct detection of characteristics of an added DUT, etc.). The tester automatically can direct the hot add in response to a user trigger.

Abstract: A semiconductor device handling apparatus handles a device under test (DUT) to bring a terminal disposed on a first surface of the DUT into contact with a contact portion of a tester comprising a tester transmitter. The semiconductor device handling apparatus includes a holder that holds a second surface of the DUT. The holder includes a holder transmitter that transmits a signal between an optical connection portion disposed on the second surface of the DUT and the tester transmitter. The holder transmitter inputs and outputs an optical signal to and from the optical connection portion.

Abstract: A socket assembly used in an electronic component test apparatus for testing a device under test (DUT) having a first device antenna, includes a socket in which the DUT is mounted, a pressing portion, disposed between an antenna unit and the socket, that presses the DUT toward the socket, the antenna unit having a first measuring antenna opposed to the socket, and a reinforcement frame on which the pressing portion is stacked. A material in the pressing portion has a lower dielectric constant than a material in the reinforcement frame.

Abstract: The disclosure describes an apparatus for testing a component, wherein the apparatus is configured to apply a magnetic field with a magnetic field orientation from a set of magnetic field orientations to the component. The apparatus is further configured to perform a test on the component in the presence of the respective magnetic fields with the respective magnetic field orientations from the set of magnetic field orientations to obtain an information characterizing an operation of the component. The apparatus is also configured to determine a test result based on the information characterizing the operation of the component in the presence of different magnetic fields with different magnetic field orientations from the set of magnetic field orientations. The disclosure also describes a method of testing and a computer-readable storage device for implementing the method and provides more efficiency in view of reliability and costs.

Abstract: A contact terminal includes one or more contact parts that contact a conductive member, a pressing member that presses the one or more contact parts relative to the conductive member, and an electrical connection member, independent from the pressing member, including one or more conductive paths connected to the one or more contact parts.

Abstract: A high frequency power divider circuit for distributing an input signal to two or more signal output ports, comprising: a rat race coupler, wherein the rat race coupler is configured to couple an input signal provided at an input port of the rat race coupler to a first output of the rat race coupler and to a second output of the rat race coupler; a first coupling structure coupled to the first output of the rat race coupler, to couple the first output of the rat race coupler with a first signal output port; and a second coupling structure coupled to the second output of the rat race coupler, to couple the second output of the rat race coupler with a second signal output port; wherein a characteristic impedance of a first transmission line portion between the input port and the first output of the rat race coupler deviates from a nominal ring impedance of the rat race coupler in a first direction, and wherein a characteristic impedance of a second transmission line portion between the input port and the second

Abstract: A device handling apparatus that handles a device under test (DUT), the DUT including a main body portion including a die, an optical fiber having one end connected to the main body portion, and a connector connected to the other end of the optical fiber, the device handling apparatus includes a holding head that holds the DUT while the optical fiber is separated from the holding head and a moving device that moves the holding head. The holding head includes a first holding portion that holds the main body portion and a second holding portion that holds the connector.

Abstract: The automated test equipment is configured to establish communication, e.g. by uploading a program to the DUT using a first interface, such as a debug interface or a generic interface having access to the processing unit for external control. A typical use case of the first interface is debug access to the DUT, which typically requires limited data rates. In the case of the invention the first interface is an ATE access for test execution. The first interface configures the DUT to open a second interface running at much higher data rate, which is higher than the first interface, for additional communication. Additionally, the second interface may have extended capabilities compared to the first interface, such as presenting its own memory to the processing unit of the DUT as a normal system memory.

Abstract: An optical connector includes one ferrule and a ferrule position retaining portion. The ferrule position retaining portion holds the one ferrule at a predetermined position. The predetermined position is a position of the one ferrule at which the one ferrule is connected with an other ferrule. The ferrule position retaining portion is arranged to hold the one ferrule such that the one ferrule is movable before and after the one ferrule is connected with the other ferrule.

Abstract: A tester system includes a test computer system for coordinating and controlling testing of a plurality of devices under test (DUTs), and a hardware interface board coupled to the test computer system and controlled by the test computer system. The hardware interface board is operable to apply test input signals to the plurality of DUTs and operable to receive test output signals from the plurality of DUTs, the hardware interface board including: a processor operable to access test pattern data for application to a DUT.

Abstract: An embodiment is an automated test equipment (ATE) for testing a device under test (DUT) which is connected to the ATE via a load board. The ATE includes a stimulus module, a measurement module, a loopback, a first switch, a second switch, and a load board interface. The load board interface includes a first radio frequency port and a second radio frequency port. The first and second radio frequency ports are configured to be coupled to the respective ports of the load board. The first switch is configured to couple the first radio frequency port to the stimulus module in a first switching state of the first switch and the second switch is configured to couple the second radio frequency port to the measurement module in a first switching state of the second switch.

Abstract: An electronic component handling apparatus that handles a DUT or a carrier accommodating the DUT, including: a pressing device that: electrically connects the DUT to a socket by pressing the DUT or the carrier toward the socket, and includes: a temperature control device that: controls a temperature of the DUT, and includes: a heater unit that is a heat source, the heater unit including: a flat heater; a first heat transfer material disposed on a first main surface of the flat heater; and a second heat transfer material disposed on a second main surface of the flat heater.

Abstract: An electronic component handling apparatus pressing the DUT against a socket electrically connected to a tester, includes: a first receiver that receives, from the tester, a first signal indicating a detection value of a temperature detection circuit; a calculator that calculates a temperature of the DUT based on the first signal; a calibrator that calibrates the calculated temperature; a second receiver that receives, from the tester, a second signal that causes the calibrator to start a first calibration; and a temperature adjuster that adjusts the temperature of the DUT. The second receiver receives the second signal before the tester turns on the DUT, once the second signal is received, the calibrator calculates a first calibrated temperature by executing the first calibration with respect to the calculated temperature, and the temperature adjuster adjusts the temperature of the DUT based on the first calibrated temperature.

Abstract: A test carrier carried in a state of accommodating a device under test (DUT) includes: a carrier body that holds the DUT, and a lid member that covers the DUT and is attached to the carrier body. The carrier body has a first through-hole for positioning that is provided to face the DUT.

Abstract: A circuit for calibrating a plurality of automated test equipment channels comprises a central measurement unit configured to provide a current to one of the ATE channels and/or to measure a current from one of the ATE channels. The central measurement unit comprises a central measurement port, which is coupled with the plurality of ATE channels via respective diodes circuited between the central measurement port of the central measurement unit and respective DUT ports of the ATE channels.

Abstract: Device testing techniques including allocating a log memory, testing a device, and storing test result during testing of the device in the allocated log memory. The allocated log memory can be accessed through an application programming interface (API) during testing of the device, wherein the allocated log memory remains unlocked during testing of the device.

Abstract: A semiconductor wafer handling apparatus moves a semiconductor wafer including a first surface on which a terminal of one or more device under tests (DUTs) is disposed and presses the terminal against a contactor of a probe card. The semiconductor wafer handling apparatus includes: a holder that holds the semiconductor wafer such that the first surface and a second surface of the semiconductor wafer are at least partially exposed; a first moving device that relatively moves the holder with respect to the probe card; a temperature adjusting device that contacts the second surface of the semiconductor wafer and adjusts a temperature of the DUTs; and a second moving device that relatively moves the temperature adjusting device with respect to the semiconductor wafer held by the holder.

Abstract: A semiconductor device handling apparatus that moves a device under test (DUT) so that a terminal on a first surface of the DUT contacts a contact part of a semiconductor device testing apparatus, the semiconductor device handling apparatus includes a holding part that holds a second surface of the DUT and an optical probe that inputs and outputs an optical signal to and from an optical connection part on the second surface of the DUT.