Abstract: A method for receiving data using an FPGA receiver circuit comprises receiving payload data from a DUT using a first rate of a plurality of line rates during a first burst, wherein the DUT is communicatively coupled to the FPGA receiver circuit. The method further comprises transitioning to a power saving state at an end of the first burst and receiving synchronization data from the DUT using a second rate of a plurality of line rates during a second burst. Further, the method comprises establishing synchronization with a clock data recovery (CDR) circuit of the FPGA receiver circuit at the second rate and receiving payload data from the DUT at the second rate.

Abstract: A sensor test apparatus having excellent versatility is provided. The sensor test apparatus 30 includes a first application unit 40 including a first application device 42 including a socket 445 to which the sensor 90 is electrically connected, and a pressure chamber 43 which applies pressure to the sensor 90, a test unit 35 which tests the sensor 90 via the socket 445, a conveying robot 33 which conveys the sensor 90 into and out of the first application unit 40, and an apparatus main body 301 which houses the first application unit 40, the test unit 35 and the conveying robot 33, and the apparatus main body 301 has an opening 306d which allows the first application unit 40 to be inserted into the apparatus main body 301 and removed from the apparatus main body 301 to an outside.

Abstract: A sensor test apparatus capable of efficiently testing a sensor is provided. A sensor test apparatus 30 which tests the pressure sensor 90 includes an application unit 40 including an application device 42 including a socket 445 to which the sensor 90 is electronically connected, a pressure chamber 43 which applies pressure to the sensor 90, and a heat sink 443,462 which applies a thermal stress to the sensor 90, the test unit 35 which tests the sensor 90 via the socket 445, and the conveying robot 33 which conveys the sensor 90 into and out of the application unit 40.

Abstract: A sensor test system having excellent throughput is provided. The sensor test system 1 includes a test apparatus group 20 including a plurality of sensor test apparatuses 30A to 30D coupled to each other so that the sensor 90 can be transferred, and each of the sensor test apparatuses 30A to 30D includes an application unit 40 including an application device 42 including a socket 445 to which the sensor 90 is electrically connected, and a pressure chamber 43 which applies a pressure to the sensor 90, a test unit 35 which tests the sensor 90 via the socket 445, and a conveying robot 33 which conveys the sensor 90 into and out of the application unit 40.

Abstract: New cooling control techniques suitable for use in the testing of devices are disclosed. The new cooling control techniques are an improvement over existing cooling control techniques because the new cooling control techniques utilize inputs that are more representative of actual thermal conditions experienced by a DUT (device under test) and/or are more representative of various other parameters, such as DUT power consumption/dissipation, during testing. Also, the new cooling control techniques offer flexibility with respect to the cooling control algorithm to employ for the DUT during testing.

Abstract: New cooling assembly suitable for use in the testing of devices is disclosed. The new cooling assembly transfers heat that is in close proximity to, within vicinity of, and/or in surrounding area adjacent to a DUT (device under test) undergoing testing to a target location that is away from the DUT. Consequently, the DUT is cooled. By employing heat pipes coupled to plates in contact with the DUT, the new cooling assembly augments cooling capacity at the DUT's location and surrounding area. Yet, the use of an ambient air flow generated by a fan is sufficient to manage and dissipate the heat transferred to the target location. Also, the new cooling assembly is readily installable in DUT testing equipment because its design is quite flexible to adapt to various requirements and space constraints of DUT testing equipment for different DUT footprints or form factors.

Abstract: In one embodiment, a testing apparatus comprises: a modularized logic unit comprising circuitry for testing a plurality of devices under test (DUTs); a DUT interface board for physically and electrically interfacing with said modularized logic unit, said DUT interface board comprising: a loadboard comprising a plurality of sockets for receiving said plurality of DUTs; and a partial enclosure for partially enclosing said plurality of DUTs; a top fan disposed adjacent to a top of said partial enclosure; and a bottom fan disposed adjacent to a bottom of said partial enclosure, wherein the top fan and the bottom fan are operable to generate a vertical ambient air flow from the bottom fan to the top fan to cool said plurality of DUTs with exposed top and bottom sides, wherein the bottom fan is operable to draw ambient air from a surrounding environment.

Abstract: A method for characterizing a FM chirp signal generated by a device under test (DUT) is disclosed. The method comprises receiving a selection of a sample frequency and chirp duration for capturing the FM chirp signal. The method also comprises down converting the FM chirp signal and capturing the FM chirp signal using a digital pin electronics card. The method comprises obtaining a plurality of period measurements from the captured FM chirp signal using a timing measurement unit (TMU) of an automated test equipment (ATE) and converting each of the plurality of period measurements into corresponding frequency values.

Abstract: A programmable logic device, such as a field programmable gate array (FPGA), is disclosed that allows for both high speed and low speed signal processing using the existing high speed transceiver. The programmable logic of the device may be programmed to include a sampling logic block that determines the low speed bit patterns from a device under test (DUT). The logic may further include a bit replication logic block that replicates bits such that the output of the device's high speed transceiver looks like a low speed signal to the DUT. The device, therefore, can communicate with the DUT at both the high and low speeds without the need for intermediate hardware.

Abstract: The present invention facilitates efficient and effective device testing and debugging. In one embodiment, a tester system includes a controller processor; a plurality of programmable accelerator circuits coupled to and controlled by the controller processor; and a plurality of load boards respectively coupled to the plurality of programmable accelerator circuits. The plurality of load boards can apply the input test signals to a plurality of devices under test (DUTs) and capture the output test signals therefrom. The plurality of programmable accelerator circuits can provide input test signals and capture output test signals. In one exemplary implementation, each of the plurality of load boards comprises: a first set of connections for transmitting input test signals to a respective DUT; a second set of connections for receiving output test signals from the respective DUT; and sideband connectors. The sideband connectors receive test related information from the DUT.

Abstract: System and method for processing a signal sampled from an output of a digital-analog converter. The method comprises: (a) transforming the input signal from time domain to frequency domain to obtain a signal having a plurality of bins; (b) estimating properties of a largest amplitude bin, except for direct current (DC) bin, in the input signal; (c) performing signal reconstruction in time domain based on the estimated properties to generate a reconstructed signal; (d) subtracting the estimated signal from the input signal to get a residual signal; (e) repeating steps (a)-(d) till a predetermined number of bins have been processed; (f) adding all the reconstructed signals and the last residual signal together to generate a sum signal; and (g) transforming the sum signal from the time domain to the frequency domain.

Abstract: A system for performing an automated test is disclosed. The method comprises programming a application programming interface (API) to control a default production flow on a tester, wherein the production flow comprises a plurality of test sequences associated with executing tests on devices under test (DUTs) connected to the tester. The method further comprises configuring the API to modify the default production flow to customize the plurality of test sequences in accordance with a user-specific API, wherein the user-specific API comprises a modification to the production flow in accordance with testing requirements of a user. Finally, the method comprises integrating the user-specific API with the API to customize the API for the user.

Abstract: To realize a multi-beam formation device that can stably machine a fine pattern using complementary lithography, provided is a device that deforms and deflects a beam, including an aperture layer having a first aperture that deforms and passes a beam incident thereto from a first surface side of the device and a deflection layer that passes and deflects the beam that has been passed by the aperture layer. The deflection layer includes a first electrode section having a first electrode facing a beam passing space in the deflection layer corresponding to the first aperture and a second electrode section having an extending portion that extends toward the beam passing space and is independent from an adjacent layer in the deflection layer and a second electrode facing the first electrode in a manner to sandwich the beam passing space between the first electrode and an end portion of the second electrode.

Abstract: A system for performing an automated test is disclosed. The system comprises a first user computer operable to load a first test plan from a first user to a control server and a second user computer operable to load a second test plan from a second user to the control server. The system further comprises a tester comprising at least one rack for deploying a plurality of primitives. The control server is communicatively coupled to the first user computer, the second user computer and to the tester, wherein the control server is operable to allocate a first subset of primitives to the first test plan and manage execution of the first test plan on the first subset of primitives, and also operable to concurrently allocate a second subset of primitives to the second test plan and manage execution of the second test plan on the second subset of primitives.

Abstract: A load board to which a socket is mounted is electrically connected to a tester. The load board includes a first optical communication unit capable of transmitting and/or receiving signals by optical wireless communication with an electronic component handling apparatus that presses a DUT against the socket.

Abstract: An electronic component handling apparatus that handles a DUT having a temperature detection circuit and presses the DUT against a socket electrically connected to a tester is provided. The electronic component includes: a temperature adjuster that adjusts a temperature of the DUT; a first receiver that receives a first signal from the tester, the first signal indicating a junction temperature of the DUT; a second receiver that receives a second signal from the tester, the second signal indicating a detection value of the temperature detection circuit; a first calculator that calculates the temperature of the DUT by using the first signal and the second signal; and a temperature controller that controls the temperature adjuster on the basis of a calculation result of the first calculator.

Abstract: A test carrier carried in a state of accommodating a device under test (DUT) includes: a carrier body that holds the DUT; and a lid member that covers the DUT and is attached to the carrier body. The carrier body has contactors provided to correspond to terminals of the DUT, external terminals electrically connected to the contactors, and a first through-hole for positioning that is provided to face the DUT. The first through-hole penetrates the carrier body so that a part of the DUT is seen from an outside through the first through-hole.

Abstract: This invention relates to an apparatus, a method and a computer program for calculating one or more scattering parameters of a linear network, the network including a number of N ports adapted to provide electric connections. The apparatus is configured to calculate, and the method includes calculating, one or more scattering parameters of the linear network, which are related to a reference impedance, on the basis of a measured electrical response at one or more ports of the linear network to an incident wave applied at a port of the linear network, measured under the condition that one or more of other ports of the linear network face a reflection coefficient ? with an amplitude ? of 0.5 or larger. The computer program is adapted to perform such a method and runs on a computer.

Abstract: A control device includes: a differential amplification circuit that amplifies a difference with respect to an input signal; and a clipping circuit that is connected to an output side of the differential amplification circuit and clips an input voltage. The differential amplification circuit includes a plurality of switching elements formed of a GaN semiconductor, and the clipping circuit includes a switching element formed of the GaN semiconductor.

Abstract: A system for performing an automated test is disclosed. The system comprises a user computer operable to load a test program from a user to a control server, wherein the test program comprises a plurality of test flows. The system further comprises a tester deploying a plurality of primitives. Further, the control server is communicatively coupled to the user computer and to the tester, wherein the control server is operable to download the test program to a primitive from the plurality of primitives, and wherein the control server is further operable to execute a first test flow from the plurality of test flows on a first DUT within the primitive and concurrently execute a second test flow from the plurality of test flows on a second DUT within the primitive.