Abstract: A tester system includes a test computer system for coordinating and controlling testing of a plurality of devices under test (DUTs), and a hardware interface board coupled to the test computer system and controlled by the test computer system. The hardware interface board is operable to apply test input signals to the plurality of DUTs and operable to receive test output signals from the plurality of DUTs, the hardware interface board including: a processor operable to access test pattern data for application to a DUT.

Abstract: An embodiment is an automated test equipment (ATE) for testing a device under test (DUT) which is connected to the ATE via a load board. The ATE includes a stimulus module, a measurement module, a loopback, a first switch, a second switch, and a load board interface. The load board interface includes a first radio frequency port and a second radio frequency port. The first and second radio frequency ports are configured to be coupled to the respective ports of the load board. The first switch is configured to couple the first radio frequency port to the stimulus module in a first switching state of the first switch and the second switch is configured to couple the second radio frequency port to the measurement module in a first switching state of the second switch.

Abstract: An electronic component handling apparatus that handles a DUT or a carrier accommodating the DUT, including: a pressing device that: electrically connects the DUT to a socket by pressing the DUT or the carrier toward the socket, and includes: a temperature control device that: controls a temperature of the DUT, and includes: a heater unit that is a heat source, the heater unit including: a flat heater; a first heat transfer material disposed on a first main surface of the flat heater; and a second heat transfer material disposed on a second main surface of the flat heater.

Abstract: A test carrier carried in a state of accommodating a device under test (DUT) includes: a carrier body that holds the DUT, and a lid member that covers the DUT and is attached to the carrier body. The carrier body has a first through-hole for positioning that is provided to face the DUT.

Abstract: An electronic component handling apparatus pressing the DUT against a socket electrically connected to a tester, includes: a first receiver that receives, from the tester, a first signal indicating a detection value of a temperature detection circuit; a calculator that calculates a temperature of the DUT based on the first signal; a calibrator that calibrates the calculated temperature; a second receiver that receives, from the tester, a second signal that causes the calibrator to start a first calibration; and a temperature adjuster that adjusts the temperature of the DUT. The second receiver receives the second signal before the tester turns on the DUT, once the second signal is received, the calibrator calculates a first calibrated temperature by executing the first calibration with respect to the calculated temperature, and the temperature adjuster adjusts the temperature of the DUT based on the first calibrated temperature.

Abstract: A circuit for calibrating a plurality of automated test equipment channels comprises a central measurement unit configured to provide a current to one of the ATE channels and/or to measure a current from one of the ATE channels. The central measurement unit comprises a central measurement port, which is coupled with the plurality of ATE channels via respective diodes circuited between the central measurement port of the central measurement unit and respective DUT ports of the ATE channels.

Abstract: Device testing techniques including allocating a log memory, testing a device, and storing test result during testing of the device in the allocated log memory. The allocated log memory can be accessed through an application programming interface (API) during testing of the device, wherein the allocated log memory remains unlocked during testing of the device.

Abstract: A coaxial cable includes an inner conductor including a central part and a conductive layer surrounding the central part, an insulator surrounding the inner conductor, and an outer conductor surrounding the insulator. The central part includes either a cavity or a portion made of resin material.

Abstract: A semiconductor wafer handling apparatus moves a semiconductor wafer including a first surface on which a terminal of one or more device under tests (DUTs) is disposed and presses the terminal against a contactor of a probe card. The semiconductor wafer handling apparatus includes: a holder that holds the semiconductor wafer such that the first surface and a second surface of the semiconductor wafer are at least partially exposed; a first moving device that relatively moves the holder with respect to the probe card; a temperature adjusting device that contacts the second surface of the semiconductor wafer and adjusts a temperature of the DUTs; and a second moving device that relatively moves the temperature adjusting device with respect to the semiconductor wafer held by the holder.

Abstract: A semiconductor wafer handling apparatus that moves a semiconductor wafer including a device under test (DUT) and presses a terminal of the DUT against a contactor of a probe card, the semiconductor wafer handling apparatus includes an optical probe that inputs and outputs an optical signal to and from an optical connection part of the DUT. The terminal is disposed on a first surface of the semiconductor wafer. The optical connection part is disposed on a second surface of the semiconductor wafer.

Abstract: A semiconductor device handling apparatus that moves a device under test (DUT) so that a terminal on a first surface of the DUT contacts a contact part of a semiconductor device testing apparatus, the semiconductor device handling apparatus includes a holding part that holds a second surface of the DUT and an optical probe that inputs and outputs an optical signal to and from an optical connection part on the second surface of the DUT.

Abstract: A measurement unit is disclosed and includes a converter unit and a processing unit is configured to provide a measurement result value, based on a first input signal and a second input signal. The converter unit is configured to provide a first digital, quantized values based on the first input signal or derived from the first input signal and the second input signal. The converter unit is further configured to provide second digital, quantized values based on the second input signal. The measurement unit is configured to change the one or more control signals of the converter unit between determination of different first values or a determination of the different second values, wherein different first values and/or different second values are provided using different converter quantization step sizes.

Abstract: Embodiments of the present invention can provide an extended NVMe driver that supports exercising virtual functions (and related physical functions) of a DUT without using a VM or hypervisor. In this way, the amount of memory and processing resources used for testing NVMe SSDs can be significantly reduced, and a large number of DUTs (e.g., up to 16 DUTs) can be tested in parallel independently. In other words, each DUT is tested in isolation, as if is the only device being tested, and there are no race conditions or competition for resources between workloads during testing.

Abstract: Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a multiple-name-space testing system comprises a load board, testing electronics, and a namespace testing tracker. The load board is configured to couple with a plurality of devices under test (DUTs). The testing electronics are configured to test the plurality of DUTs, wherein the testing electronics are coupled to the load board. The controller is configured to direct testing of multiple-name-spaces across the plurality of DUTs at least in part in parallel. The controller can be coupled to the testing electronics. The namespace testing tracker is configured to track testing of the plurality of DUTs, including the testing of the multiple-name-spaces across the plurality of DUTs at least in part in parallel. In one embodiment, the DUTs are NVMe SSD devices.

Abstract: Embodiments of the present invention can selectively enable 16 lane (×16) or 8 lane (×8) device testing using multiplexor circuitry disposed between a CXL1.1 CPU and the DUTs during testing. In this way, parallelism and testing efficiency are significantly improved compared to existing approaches that can only test devices using 8 lanes of the CXL 1.1 CPU.

Abstract: A temperature adjustment system for adjusting a temperature of a DUT electrically connected to a socket includes a first temperature adjustment device that supplies a fluid to an internal space in either the socket or a contact member that contacts the DUT when the DUT is pressed against the socket and a second temperature adjustment device that adjusts a temperature of an atmosphere in a chamber in which the socket and the contact member are disposed. The first temperature adjustment device includes a first supplier that supplies a first fluid and includes one or more connectors connected to one or more supply sources that supply the first fluid and a heat exchanger disposed between the one or more connectors and the internal space. The heat exchanger has a heat exchange part exposed in the chamber and exchanges heat between the first fluid and the atmosphere in the chamber.

Abstract: Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a flexible sideband support system comprises a load board, testing electronics coupled to the load board, a controller coupled to the testing electronics. The load board is configured to couple with a plurality of devices under test (DUTs), wherein the load board includes in-band testing ports and sideband testing ports. The testing electronics is configured to test the plurality of DUTs, wherein a portion of testing electronics are organized in sideband resource groups. The controller is configured to direct testing of the DUTs, wherein the controller is coupled to the testing electronics and the controller directs selective allocation of the testing electronics in the sideband resource groups to various testing operations of the DUTs.

Abstract: Efficient and effective testing systems and methods are presented. In one embodiment, a test system includes: a user interface configured to enable user interaction with the system; a test board configured to communicatively couple with a plurality of devices under test (DUTs), wherein the DUTs are compute express link (CXL) protocol compliant; and a tester configured to direct testing of the plurality of DUTs, wherein the tester manages testing of the plurality of DUTs, including managing flexible and independent parallel testing across the plurality of DUTs. In one exemplary implementation, the tester generates and manages workloads independently for DUTs included in the plurality of DUTs. The DUTs can be memory devices the tester is configured to test different memory spaces in parallel. The different memory spaces can have various implementations (e.g., included in the plurality of DUTs, different memory spaces are within one of the DUTs included in the plurality of DUTs, etc.).

Abstract: An electrical filter structure for forwarding an electrical signal from a first port, e.g. P1, to a second port, e.g. P2, in a frequency selective manner, wherein the filter is a microwave filter, the electrical filter structure comprising: a plurality of pairs of an open stub and a short-circuited stub coupled electrically in parallel to a transmission line comprising a plurality of transmission line portions at a plurality of respective junctions between adjacent transmission line portions, e.g.

Abstract: The automated test equipment is configured to establish communication, e.g. by uploading a program to the DUT using a first interface, such as a debug interface or a generic interface having access to the processing unit for external control. A typical use case of the first interface is debug access to the DUT, which typically requires limited data rates. In the case of the invention the first interface is an ATE access for test execution. The first interface configures the DUT to open a second interface running at much higher data rate, which is higher than the first interface, for additional communication. Additionally, the second interface may have extended capabilities compared to the first interface, such as presenting its own memory to the processing unit of the DUT as a normal system memory.