Patents Assigned to Advantest Corporation
  • Patent number: 10324127
    Abstract: An electronic component handling apparatus (10) is provided which can improve the operation rate. The electronic component handling apparatus (10) includes: a contact arm (300) having a holding part (380) configured to hold a DUT (10A), the contact arm (300) being configured to press the DUT (10A) against a socket (410); an alignment device (200) including a camera (221) and a operation unit (230), the camera (221) being configured to image the DUT (10A) to acquire image information, the operation unit (230) being configured to adjust a position of the holding part (380) within a range of a maximum alignment amount (ALmax); and a control device (105) configured to control the contact arm (300) and the alignment device (200). When a predetermined condition is not satisfied, the control device (105) controls the contact arm (300) and the alignment device (200) so as to perform preliminary alignment work at least once.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: June 18, 2019
    Assignee: ADVANTEST CORPORATION
    Inventors: Yasuyuki Kato, Masataka Onozawa, Keisuke Nitta
  • Patent number: 10297043
    Abstract: An apparatus for detecting an attitude of electronic components. The electronic components include an electronic component having a plurality of terminals. The apparatus includes a storage and an image processor. The image processor is configured to: extract a binarized image from an image acquired by an imaging device; perform image matching between a terminal in the binarized image and a terminal in a model image to extract attitude candidates of image matching; obtain coordinates of a corner part of the plurality of terminals from the binarized image of the electronic component; select an attitude candidate from among the attitude candidates of image matching; and output the attitude candidate as a detected attitude of the electronic component.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: May 21, 2019
    Assignee: ADVANTEST CORPORATION
    Inventors: Masataka Onozawa, Aritomo Kikuchi
  • Patent number: 10297339
    Abstract: Example features or aspects of the present invention are described in relation to a small, quiet integrated cooling system for an apparatus for testing electronic devices. Characteristics of the test apparatus including a low noise output, low power consumption and a compact size with a small spatial and volume footprint are selected for deployment and use in a an office like environment. The test apparatus comprises a chassis frame and a cooler frame disposed within the chassis frame and thus integrated within the test apparatus, which has a reduced form factor suitable for the in-office deployment. Embodiments offer the ability to maintain the working fluid at a constant temperature.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: May 21, 2019
    Assignee: Advantest Corporation
    Inventors: Brent Thordarson, John W. Andberg, Koei Nishiura
  • Patent number: 10288681
    Abstract: An automated test equipment (ATE) apparatus is presented. The apparatus comprises a computer system comprising a system controller, wherein the system controller is communicatively coupled to a site module board comprising a tester processor and an FPGA wherein the system controller is operable to transmit instructions to the tester processor, and wherein the tester processor is operable to generate commands and data from the instructions for coordinating testing of a device under test (DUT) wherein the site module board comprises a compact form factor suitable for use during prototyping, and wherein the site module board is operable to be coupled with a DUT. Further, the FPGA is communicatively coupled to the tester processor, wherein the FPGA comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the tester processor for testing the DUT.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: May 14, 2019
    Assignee: Advantest Corporation
    Inventors: Duane Champoux, Mei-Mei Su
  • Patent number: 10255155
    Abstract: Embodiments provide a scheduler for scheduling test times of a plurality of tester software environments for an automatic test equipment. The scheduler is configured to automatically assign test times to the plurality of tester software environments, to acquire test instructions from a tester software environment of the plurality of tester software environments to which a current test time is assigned, to control the automatic test equipment to perform a test according to the test instructions in order to obtain test results, and to provide the test results to the tester software environment of the plurality of tester software environments to which the current test time is assigned.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: April 9, 2019
    Assignee: Advantest Corporation
    Inventor: Peter Schinzel
  • Publication number: 20190101587
    Abstract: [Object] Provided is an electronic component handling apparatus capable of improving test quality. [Solving Means] An electronic component handling apparatus 20 handling a DUT 90 having a temperature detection circuit 92 and pressing the DUT 90 against a socket 11 electrically connected to a tester 10 includes: a temperature adjuster 40 adjusting a temperature of the DUT 90, a first receiver 51 receiving a first signal indicating a junction temperature Tj of the DUT 90 from the tester 10, a second receiver 52 receiving a second signal indicating a detection value Tj+c of the temperature detection circuit 92 from the tester 10, a first calculator 54 calculating a temperature Tj? of the DUT 90 by using the first signal and the second signal, and a temperature controller 55 controlling the temperature adjuster 40 on the basis of a calculation result of the first calculator 54.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Applicant: Advantest Corporation
    Inventor: Katsuhiko Watanabe
  • Patent number: 10243408
    Abstract: An automatic tuning assist circuit is coupled with a transmission antenna. Multiple switches SW and a first auxiliary capacitor CA are arranged between a first terminal and a second terminal of the automatic tuning assist circuit. A first control unit is configured to switch on and off the multiple switches SW in synchronization with a driving voltage VDRV. A power supply is configured to apply the driving voltage VDRV across a series circuit that comprises the transmission antenna and the automatic tuning assist circuit.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: March 26, 2019
    Assignee: ADVANTEST CORPORATION
    Inventors: Yuki Endo, Yasuo Furukawa
  • Patent number: 10241146
    Abstract: Presented embodiments facilitate efficient and effective access to a device under test. In one embodiment, a test system comprises: a device interface board (DIB) configured to interface with a device under test (DUT); and a primitive configured to control the device interface board and testing of the device under test. The primitive is an independent self contained test control unit comprising: a backplane interface configured to couple with the device interface board; a power supply component configured to control power to the backplane interface; and a site module configured to control testing signals sent to the device interface board and device under test. The site module is reconfigurable for different test protocols. The primitive can be compatible with a distributed testing infrastructure. In one exemplary implementation, the primitive and device interface board are portable an operable to perform independent testing unfettered by other control components.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: March 26, 2019
    Assignee: Advantest Corporation
    Inventors: Mei-Mei Su, Ben Rogel-Favila
  • Patent number: 10234498
    Abstract: An automated test equipment for testing a device under test includes a control unit and a plurality of tester subunits. The control unit is configured to put the tester subunits in a state of lower activity in dependence on a current demand on the test resources.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: March 19, 2019
    Assignee: ADVANTEST CORPORATION
    Inventors: Jonas Horst, Heinz Nuessle, Bernd Laquai
  • Patent number: 10228362
    Abstract: A measurement apparatus is provided that measures a current signal IDUT that flows through a device under test. A transimpedance amplifier converts the current signal IDUT into a voltage signal VOUT. A digitizer converts the voltage signal VOUT into first digital data. A digital signal processing unit performs signal processing on the first digital data, and controls the measurement apparatus. The measurement apparatus has a configuration comprising two separate modules, i.e., a probe module which is located in the vicinity of the device under test during a measurement, and a backend module connected to the probe module via at least one cable. The transimpedance amplifier is built into the probe module.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: March 12, 2019
    Assignee: ADVANTEST CORPORATION
    Inventor: Yasuhide Kuramochi
  • Patent number: 10229912
    Abstract: According to the present invention, a semiconductor device includes a semiconductor layer, a source electrode provided in the semiconductor layer, a drain electrode provided in the semiconductor layer and disposed away from the source electrode, a first gate electrode provided between the source electrode and the drain electrode and a second gate electrode provided between the source electrode and the drain electrode, the second gate electrode having at least a part thereof located closer to the drain electrode than the first gate electrode. The semiconductor layer includes a first facing part that is a part facing the first gate electrode; and a second facing part that is a part facing the second gate electrode. The first facing part does not conduct when a first gate voltage is 0 V or less. The second facing part does not conduct when a second gate voltage is 0 V or less.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: March 12, 2019
    Assignee: ADVANTEST CORPORATION
    Inventors: Taku Sato, Kazuya Uryu, Kazuyuki Shouji
  • Publication number: 20190041470
    Abstract: [Object] Provided is a magnetic sensor testing device capable of preventing performance of an electromagnet from greatly changing due to heat applied to a magnetic sensor. [Solving Means] A magnetic sensor testing device includes electromagnets 50 and 60 that apply a magnetic field to a magnetic sensor, temperature regulators 30 and 40 that regulate a temperature of the magnetic sensor by locally applying heat to the magnetic sensor, and a controller that controls the electromagnets 50 and 60 and the temperature regulators 30 and 40, in which the controller tests the magnetic sensor in a state in which the magnetic field is applied to the magnetic sensor by the electromagnets 50 and 60 while the heat is applied to the magnetic sensor by the temperature regulators 30 and 40.
    Type: Application
    Filed: July 24, 2018
    Publication date: February 7, 2019
    Applicant: Advantest Corporation
    Inventors: Yuki Endo, Aritomo Kikuchi, Shigeo Nakamura
  • Patent number: 10162007
    Abstract: Automated test equipment (ATE) capable of performing a test of semiconductor devices is presented. The ATE comprises a computer system comprising a system controller communicatively coupled to a tester processor. The system controller is operable to transmit instructions to the processor and the processor is operable to generate commands and data from the instructions for coordinating testing of a plurality of devices under test (DUTs). The ATE further comprises a plurality of FPGA components communicatively coupled to the processor via a bus. Each of the FPGA components comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the processor for testing one of the DUTs. Additionally, the tester processor is configured to operate in one of several functional modes, wherein the functional modes are configured to allocate functionality for generating commands and data between the processor and the FPGA components.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: December 25, 2018
    Assignee: ADVANTEST CORPORATION
    Inventors: Gerald Chan, Eric Kushnick, Mei-Mei Su, Andrew Steele Niemic
  • Patent number: 10161962
    Abstract: In an embodiment, a universal test cell includes a plurality of test slots configured to receive a plurality of universal test containers each including similar dimensions. Each universal test container is configured to enclose each of a plurality of different devices to test. Each universal test container includes an external electrical interface configured to couple to each of the plurality of different devices to test. The universal test cell is configured to test the plurality of different devices while each is located within a universal test container of the plurality of universal test containers. The universal test cell includes a plurality of universal electrical interfaces that are each configured to couple with the external electrical interface of each universal test container.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: December 25, 2018
    Assignee: Advantest Corporation
    Inventors: Ben Rogel-Favila, Roland Wolff, Eric Kushnick, James Fishman
  • Patent number: 10161993
    Abstract: Automated test equipment capable of performing a high-speed test of semiconductor devices is presented. The automated test equipment apparatus comprises a computer system comprising a tester processor, wherein the tester processor is communicatively coupled to a plurality of FPGA components. Each of the plurality of FPGA components is coupled to a memory module and comprises: an upstream port operable to receive commands and data from the tester processor; a downstream port operable to communicate with a respective DUT from a plurality of DUTs; and a plurality of hardware accelerator circuits, wherein each of the accelerator circuits is configured to communicate with one of the plurality of DUTs. Each of the plurality of hardware accelerator circuits comprises a pattern generator circuit configurable to automatically generate test pattern data and a comparator circuit configured to compare data.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: December 25, 2018
    Assignee: Advantest Corporation
    Inventors: John Frediani, Andrew Niemic
  • Publication number: 20180356460
    Abstract: An electronic component handling apparatus (10) is provided which can improve the operation rate. The electronic component handling apparatus (10) includes: a contact arm (300) having a holding part (380) configured to hold a DUT (10A), the contact arm (300) being configured to press the DUT (10A) against a socket (410); an alignment device (200) including a camera (221) and a operation unit (230), the camera (221) being configured to image the DUT (10A) to acquire image information, the operation unit (230) being configured to adjust a position of the holding part (380) within a range of a maximum alignment amount (ALmax); and a control device (105) configured to control the contact arm (300) and the alignment device (200). When a predetermined condition is not satisfied, the control device (105) controls the contact arm (300) and the alignment device (200) so as to perform preliminary alignment work at least once.
    Type: Application
    Filed: June 8, 2017
    Publication date: December 13, 2018
    Applicant: ADVANTEST CORPORATION
    Inventors: Yasuyuki KATO, Masataka ONOZAWA, Keisuke NITTA
  • Patent number: 10151822
    Abstract: A tester including a source and measuring device and a TX port connected to the source and measuring device is provided. The tester is configured to determine a source reflection coefficient using an extension circuit. The extension circuit includes a TX port connectable to the source and measuring device, a termination switch and a calibration device providing one or more terminations, wherein each of the terminations is individually connectable to the TX port by the termination switch, wherein one of the terminations is a power sensor. The source and measuring device is configured to measure one or more reflection coefficients at the TX port for the one or more terminations provided by the calibration device including the reflection coefficient for the power sensor. The tester is configured to determine the source reflection coefficient based on the one or more measured reflection coefficients including the measured reflection coefficient for the power sensor.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: December 11, 2018
    Assignee: Advantest Corporation
    Inventor: Giovanni Bianchi
  • Patent number: 10145931
    Abstract: A tester including a source and measuring device and a TX port connected to the source and measuring device is configured to determine a source reflection coefficient using an extension circuit. The extension circuit includes a calibration device having a power sensor. The calibration device is configured to provide a plurality of different terminations at the TX port. The tester is configured to calibrate a source power of the source and measuring device using the determined source reflection coefficient and the power sensor.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: December 4, 2018
    Assignee: ADVANTEST CORPORATION
    Inventor: Andy Richter
  • Patent number: 10114067
    Abstract: A structure for signal transmission is disclosed. The structure comprises a first plurality of waveguides tightly disposed together and disposed substantially in parallel with each other, each of said waveguides having a first opening and a second opening, wherein each first opening is operable to align with a patch antenna, and wherein the first plurality of waveguides is disposed adjacent to a socket. The integrated structure further comprises the socket which comprises an opening operable to support an insertion of a device under test (DUT), wherein the DUT is communicatively coupled to a plurality of microstrip transmission lines on a printed circuit board (PCB) underlying the socket for transmitting test signals from the DUT, wherein each of the microstrip transmission lines is electrically coupled to a respective patch antenna. Further, the first plurality of waveguides and the socket are integrated into a single plastic or metal structure.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: October 30, 2018
    Assignee: ADVANTEST CORPORATION
    Inventors: Daniel Lam, Don Lee, Roger McAleenan, Kosuke Miyao
  • Patent number: 10114075
    Abstract: System and method for performing scan test on multiple IC devices by site-multiplexing. Multiple test sites of an ATE are coupled to multiple DUTs through a multiplexer. A scan test includes a scan-in/out phase and consecutive launch/capture cycles. Each site performs scan in/out in parallel on the corresponding DUT. In each launch/capture cycle, a respective site drives/captures data from a DUT while the remaining sites are inactive. The multiplexer allows the active site to borrow test channels assigned to other test sites such that all the test data of a DUT can be driven/captured in the launch capture cycle despite the test channel limitation of the active test site. As the tester channels receive interleaved data of the multiple sites, each strobe edge of a receive channel is assigned to a particular test site and used to quickly identify a failure site without post-processing test data.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: October 30, 2018
    Assignee: Advantest Corporation
    Inventor: Matthias Werner