Patents Assigned to Agere Systems Guardian Corp.
  • Patent number: 6420714
    Abstract: An apparatus for projection lithography is disclosed. The apparatus has at least one magnetic doublet lens. An aperture scatter filter is interposed between the two lenses of the magnetic doublet lens. The aperture scatter filter is in the back focal plane of the magnetic doublet lens system, or in an equivalent conjugate plane thereof. The apparatus also has two magnetic clamps interposed between the two lenses in the magnetic doublet lens. The clamps are positioned and configured to prevent substantial overlap of the magnetic lens fields. The magnetic clamps are positioned so that the magnetic fields from the lenses in the magnetic doublet lens do not extend to the aperture scatter filter.
    Type: Grant
    Filed: June 9, 2000
    Date of Patent: July 16, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Victor Katsap, Eric Munro, John Andrew Rouse, Warren K Waskiewicz, Xieqing Zhu
  • Patent number: 6421430
    Abstract: A telephone line interface or data access arrangement (DAA) includes a shunt regulator in series with a line modulator. A sense resistor is placed in series between the shunt regulator and line modulator to provide a measurement of an amount of noise in the DAA shunt regulator, which is fed back to the line modulator. The line modulator is capable of adjusting the AC modulation and DC termination presented to the telephone line. The method includes drawing power from the telephone line using a shunt regulator, modulating the telephone line in series with the shunt regulator, sensing a level of noise in the shunt regulator, and feeding back the sensed level of noise to the line modulator.
    Type: Grant
    Filed: February 23, 1998
    Date of Patent: July 16, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Keith Eugene Hollenbach, Donald Raymond Laturell, Steven Brooke Witmer
  • Patent number: 6418220
    Abstract: A network interface circuit employing differentially driven capacitive couplings across a high voltage isolation boundary and in which a &Sgr;/&Dgr; CODEC is positioned on the line side of the high voltage interface. In this manner, only four wires cross the high voltage boundary, namely differential pairs for transmit data and receive data. The transfer functions for setting AC and DC parameters, such as impedance matching, are provided by digital filters. Further, with the CODEC on the line side of the high voltage isolation interface, the data which crosses the interface is modulated at the &Sgr;/&Dgr; data rate and, thus, capacitive coupling can be used across the high voltage isolation boundary without the loss of DC data.
    Type: Grant
    Filed: April 16, 2001
    Date of Patent: July 9, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Jonathan Herman Fischer, Donald Raymond Laturell, Keith Eugene Hollenbach, Steven Brooke Witmer
  • Patent number: 6417087
    Abstract: A process for forming a dual damascene bond pad within an integrated circuit produces a bond pad which is resistant to stress effects and which therefore allows for the bond pad to be formed over active circuitry. The process includes forming a dual damascene structure by forming a bond pad opening having a barrier layer film on the bottom surface of the upper portion of the opening, and forming vias which extend downwardly through the bottom surface. The process produces a bond pad which is resistant to stress effects such as cracking which can be produced when bonding an external wire to the bond pad. Leakage currents between the bond pad and the underlying circuitry are prevented.
    Type: Grant
    Filed: December 16, 1999
    Date of Patent: July 9, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Sailesh Chittipeddi, William Thomas Cochran, Yehuda Smooha
  • Patent number: 6417717
    Abstract: A unique hierarchical multiplexer is employed to multiplex signals read out from analog array elements one at a time to an output. In an embodiment of the invention, the multiplexer switching elements, i.e., switches, are arranged in groups in a hierarchical, i.e., tree, configuration. In the tree configuration for a given analog array size, output capacitance is significantly reduced because each analog array element and its associated buffer amplifier drive fewer switches than in other configurations. The lower capacitance reduces any resulting FPN and the resulting lower analog array element and buffer amplifier drive current reduces power dissipation. The reduced capacitance also decreases the transient settling time interval.
    Type: Grant
    Filed: December 31, 1998
    Date of Patent: July 9, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventor: Marc J. Loinaz
  • Patent number: 6417528
    Abstract: The invention is a semiconductor avalanche photodetector including an essentially undoped multiplication layer; a thin, undoped light absorbing layer; and a doped waveguide layer which is separate from the light absorbing layer and is capable of coupling incident light into the light absorbing layer.
    Type: Grant
    Filed: January 28, 2000
    Date of Patent: July 9, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventor: Aaron Eugene Bond
  • Patent number: 6414383
    Abstract: An integrated electronic device package includes an enclosing structure and a substrate secured within the enclosing structure. At least one first electrical connector protrudes through a first face of the enclosing structure. At least one integrated circuit chip is included within the enclosing structure. The at least one integrated circuit chip is mechanically connected to the substrate and electrically connected to the at least one first electrical connector. Radio-frequency signals are emitted from the at least one integrated circuit chip. A first radiation absorbing device is disposed within the enclosing structure and between the at least one integrated circuit chip and a second face of the enclosing structure.
    Type: Grant
    Filed: July 16, 1999
    Date of Patent: July 2, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventor: Darren Lloyd Stout
  • Patent number: 6412680
    Abstract: A BGA ball mount line with a dual in-line mounter flowing into one reflow oven and one in-line cleaner. The dual in-line mounter comprises a first ball mount cell and a second ball mount cell. The second ball mount cell is parallel to and a mirror image of the first ball mount cell. The first ball mount cell and the second ball mount cell can be run by a single operator located between them. In one embodiment of the invention, the BGA ball mount line with dual in-line mounters is implemented in three phases to provide a smooth transition. In the first phase, a proto-line is set-up with a first ball mount cell, a loading cell, a diverter cell, and an unloading cell, to optimize the first ball mount cell. In the second phase, a reflow oven and a flux cleaner are added to form a production line. In the third phase, a second ball mount cell is added to form a BGA ball mount line with a dual in-line mounter.
    Type: Grant
    Filed: September 26, 2000
    Date of Patent: July 2, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Kok Hua Chua, Suharto Leo, Hak Meng Tan, Yew Chung Wong
  • Patent number: 6415369
    Abstract: A method and apparatus allowing efficient access control to a common data bus by including an isolation device to separate the common data bus, a priority-based arbiter to control access to the internal portion of the common data bus including a processor or other bus master, and a time slot arbiter to control access to the external portion of the common data bus including multiple bus masters, an external memory interface, etc. The common external memory may be allocated for exclusive or non-exclusive use by the various devices utilizing either portion of the isolated common data bus. External devices accessing the external memory may communicate directly with one or more bus masters, e.g., on the internal portion of the common data bus.
    Type: Grant
    Filed: August 29, 2000
    Date of Patent: July 2, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Sucheta Sudhir Chodnekar, Frederick Harrison Fischer, Kenneth Daniel Fitch, Avinash Velingker, James Frank Vomero, Shaun Patrick Whalen
  • Patent number: 6410974
    Abstract: The present invention provides for a method of manufacturing a simplified high Q inductor substrate and a semiconductor device having that substrate. The method for manufacturing the simplified high Q inductor substrate preferably includes forming a base substrate over a semiconductor wafer, wherein the base substrate has a given dopant concentration and then forming an epitaxial (EPI) layer over the base substrate. The EPI layer includes epitaxially forming a first doped region in the EPI layer over the base substrate and then epitaxially forming a second doped region in the EPI layer over the first doped region. The first doped region has a dopant concentration greater than the given dopant concentration of the base substrate, and the second doped region has a dopant concentration less than the first doped region.
    Type: Grant
    Filed: March 5, 2001
    Date of Patent: June 25, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Jerome Tsu-Rong Chu, John D. LaBarre, Wen Lin, Blair Miller
  • Patent number: 6410416
    Abstract: An article is disclosed having a non-planar surface with a high-resolution pattern formed thereon, particularly a distributed-feedback (DFB) ridge waveguide laser. An elastomeric member having relief patterns on its surface is used to print or mold a pattern directly onto the non-planar surface of the waveguide. A range of materials disposed on such non-planar surfaces can thus be patterned at high resolution to provide devices with sub-micron features at low cost with potential applications in optoelectronics. For example, a plastic laser based on molded organic gain materials may be made.
    Type: Grant
    Filed: May 28, 1999
    Date of Patent: June 25, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Ananth Dodabalapur, John A. Rogers, Richart Elliott Slusher
  • Patent number: 6411757
    Abstract: A waveguide structure for use with a pump laser is disclosed that is designed to counteract the decrease in pump power density. The waveguide structure may comprise an erbium-doped waveguide amplifier, a nonlinear waveguide wavelength converter device, or an optical fiber. The waveguide structure has a waveguide region that is tapered over a pump propagation distance, said distance being defined as a predetermined distance between a first pump site and a second pump site over which the pump light is propagated for signal amplification or conversion. The taper reduces the depletion in pump power as compared with prior art systems and may be kept substantially constant over the pump propagation length, thereby counteracting pump depletion.
    Type: Grant
    Filed: February 14, 2000
    Date of Patent: June 25, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Igal M. Brener, Gadi Lenz, Joseph Shmulovich
  • Patent number: 6411236
    Abstract: A programmable priority encoder having a plurality of request inputs and a corresponding plurality of acknowledge outputs. A configurable priority encoder subunit implements one of a plurality of priority schemes in response to a priority control word corresponding to the priority scheme. The configurable priority encoder subunit acknowledges, on a corresponding one of the acknowledge outputs, a request having a highest priority, in the priority scheme, of all current requests on the plurality of request inputs.
    Type: Grant
    Filed: October 18, 1999
    Date of Patent: June 25, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventor: Bahram Ghaffarzadeh Kermani
  • Patent number: 6411976
    Abstract: An N-stage finite impulse response (FIR) filter embodying the invention includes a first filter section whose filter coefficients are made either 1 or zero (rather than 1 and −1) in order to produce a first output (i.e., C1) and a second filter section for producing a second output (i.e., C2), which when combined (added to or subtracted from) with the first output produces an output function (i.e., Cn) which is equal to that produced by an N-stage FIR filter implementing filter coefficients having a value of either 1 or −1.
    Type: Grant
    Filed: August 10, 1998
    Date of Patent: June 25, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Richard Adam Cesari, Xiao-An Wang
  • Patent number: 6412029
    Abstract: A method and apparatus for communicating transmit and receive data between a digital signal processor and the baseband processing circuitry in a digital communications station such as a digital cellular telephone. The invention utilizes a transmit buffer and a receive buffer for smoothing out the flow of data. TRANSMIT BUFFER EMPTY and RECEIVE BUFFER FULL interrupts indicating the need for data to be retrieved from the transmit buffer or sent to the receive buffer, respectively, are serviced by a DMA with translation circuitry rather than the DSP. The DMA with translation circuitry intercepts the interrupts and services them by transferring data directly to or from the DSP's RAM without disturbing the DSP. The translation circuitry also arbitrates between TRANSMIT BUFFER EMPTY and RECEIVE BUFFER FULL interrupts so as to service the RECEIVE BUFFER FULL interrupts first since they have stricter timing requirements.
    Type: Grant
    Filed: April 29, 1999
    Date of Patent: June 25, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Hussein K. Mecklai, Andrew Lawrence Webb
  • Patent number: 6410986
    Abstract: A titanium nitride barrier within an integrated contact structure is formed as multi-layered stack. The multi-layering of the titanium nitride thus provides improved junction integrity since the multi-layer structure exhibits improved mechanical stability when compared to conventional single layer arrangements. The multi-layer titanium nitride barrier may be used as either a conventional interconnect metallization or as a nucleation structure within a tungsten plug. The multi-layer structure may be formed to include an overall thickness less than a conventional single layer, yet provide for improved stress accommodation, resulting in eliminating micro-cracks within the titanium nitride (and as a result eliminating the un-wanted diffusion of aluminum or tungsten precursors through the titanium nitride).
    Type: Grant
    Filed: December 22, 1998
    Date of Patent: June 25, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Sailesh Mansinh Merchant, Pradip Kumar Roy
  • Patent number: 6411751
    Abstract: Signal losses in an optical cross-connect having steerable switching elements for routing optical signals are substantially reduced by controllably and selectively training the steerable switching elements as a function of measured input and output power of a cross-connected optical signal. More specifically, adjustments to the alignment of one or more steerable switching elements associated with a particular cross-connection are performed in a non-intrusive manner to increase the optical signal power in an optical signal while maintaining an active cross-connection of the optical signal. In one illustrative embodiment, optical monitoring arrangements monitor the optical signal power of optical signals coupled to the cross-connect inputs and outputs. The cross-connect includes a switching fabric comprising a plurality of steerable MEMS mirror elements used as switching elements for controllably and selectively directing the light beams within the cross-connect.
    Type: Grant
    Filed: October 6, 2000
    Date of Patent: June 25, 2002
    Assignees: Lucent Technologies Inc., Agere Systems Guardian Corp.
    Inventors: Randy Clinton Giles, Albert M Gottlieb, David Thomas Neilson
  • Patent number: 6411979
    Abstract: A digital circuit for computing a function consisting of sums and differences of the products of a first vector of N multipliers and a second vector of M multiplicands, where at least one of N and M is greater than one include N multibit recoding circuits and M multiples generator circuits. Each recoding circuit receives a respective multiplier as input and produces a radix-2k signed digit representation of the multiplier as output. Each multiples generator receives a respective multiplicand as input and producing multiples of the multiplicand between one and 2k−1 as output. The output of N recoding circuits and M multiples generator circuits are fed to an N×M array of partial product summers. Each partial product summer produces a respective product output, the set of outputs of the partial product summers comprising the product of each of the multipliers with each of the multiplicands.
    Type: Grant
    Filed: June 14, 1999
    Date of Patent: June 25, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventor: Alan Joel Greenberger
  • Patent number: 6409829
    Abstract: Integrated circuit devices are formed in a substrate wafer using selective epitaxial growth (SEG). Non-uniform epitaxial wafer thickness results when the distribution of SEG regions across the surface of the wafer is non-uniform, resulting in loading effects during the growth process. Loading effects are minimized according to the invention by adding passive SEG regions thereby giving a relatively even distribution of SEG growth regions on the wafer. The passive regions remain unprocessed in the finished IC device.
    Type: Grant
    Filed: December 15, 1999
    Date of Patent: June 25, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: John Joseph Bastek, Thomas J. Krutsick, Robert D. Plummer
  • Patent number: 6410419
    Abstract: Interconnects in porous dielectric materials are coated with a SiC-containing material to inhibit moisture penetration and retention within the dielectric material. Specifically, SiC coatings doped with boron such as SiC(BN) show particularly good results as barrier layers for dielectric interconnects.
    Type: Grant
    Filed: August 7, 2000
    Date of Patent: June 25, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Sailesh Mansinh Merchant, Sudhanshu Misra, Pradip Kumar Roy