Abstract: The present invention provides a method for tuning a thin film resonator (TFR) filter comprising a plurality of TFR components formed on a substrate. Each of the TFR components has a set of resonant frequencies that depend on material parameters and construction. TFR bandpass filter response for example can be produced by shifting the set of resonant frequencies in at least one of the series branch TFR components so as to establish the desired shape of the bandpass response and the desired performance of the filter. The shifting may be advantageously performed by removing piezoelectric material from the series branch TFR component, providing a TFR filter with bandwidth and attenuation advantages over that conventionally achieved by down-shifting resonant frequency sets of the shunt TFR components by adding metal material.

Abstract: Disclosed is a lithographic method utilizing a phase-shifting mask having a pattern comprising a plurality of substantially transparent regions and a plurality of substantially opaque regions wherein the mask pattern phase-shifts at least a portion of incident radiation and wherein the phases are substantially equally spaced, thereby increasing resolution of a given lithographic system. Further disclosed is a method for fabricating a semiconductor device utilizing the phase-shifting mask.

Abstract: A diffusion preventing barrier spike is disclosed. The spike prevents diffusion of dopants into another layer without forming a pn junction in the layer. The spikes are illustratively Al or an aluminum containing material such as AlAs and have a thickness on the order of 1 nm. The spikes of the present invention may be used to stop dopant diffusion out of a doped layer in a variety of III-V semiconductor structures, such a InP-based PIN devices.

Abstract: A chemical mechanical polishing (CMP) system includes a polishing device including a polishing article. The polishing device holds the semiconductor wafer and provides relative movement between the semiconductor wafer and the polishing article with a slurry therebetween. The CMP system also includes a slurry processor for processing used slurry from the polishing device and for delivering processed slurry to the polishing device. The slurry processor including a metal separator for separating metal particles, polished from the semiconductor wafer, from the used slurry. The slurry can be continuously recirculated during a CMP process without damaging and/or contaminating the layers of the semiconductor wafer.

Abstract: In accordance with the invention, an integrated dual wavelength transceiver comprises a multilayer monolithic structure that functions as an optical waveguide, a photodetector, and a light emitter. In an alternative embodiment, second spaced apart portion on the same substrate can provide an amplifier to amplify electrical signals generated by the photodetector.

Abstract: A system for measuring the thickness of a wafer while it is being thinned this disclosed. The system and method provide integrating an optical reflectometer into a common wafer thinning apparatus. Using reflected optical signals from the top and bottom of the wafer, the thickness of the wafer is determined with time based calculations in real-time while thinning is occurring. Once the desired thickness has been reached, the thinning operation is halted. By performing the measurement in-situ, this system and a method prevent scrapping of wafers which are overthinned and the reloading of wafers which are too thick. Since an optical reflectometer is used, the measurement is contactless, and thus prevents possible damage to wafers during measurement.

Abstract: The invention is a semiconductor device and method of fabricating the device. The device includes a semiconductor substrate with an active region, and a low dielectric constant insulating layer formed over the substrate. An additional insulating layer is formed over the low dielectric constant layer by a low temperature deposition, such as ion beam assistance deposition. A metal layer can then be formed over the additional layer using lift-off techniques. The metal layer can be patterned to form a bond pad which may be displaced from the area over the active region. Wire bonds can be made on the bond pad using ultrasonic energy.

Abstract: The invention reflects a recognition that prior art templates for colloidal crystal formation do not provide the expected level of three-dimensional periodicity, and further provides a process using an improved template, by which extremely high-quality colloidal crystals are able to be formed. Specifically, the colloidal template of the invention is designed such that the colloidal particles are induced to settle into the desired locations, unlike in prior art templates, thereby settling in an ordered manner.

Abstract: During fabrication of components for optical devices, chamfers (or radii) are formed at the edges of the surfaces of the components that are to be subjected to a friction process, such as lapping. After the chamfers are formed, the component is plated, with the plating following the contour of the chamfers. Material is then removed from the surface using a friction process. Because the plating follows the contour of the chamfer, it forms an angle to the lapping stone or wheel used during lapping, where the angle of the plating to the lapping stone is approximately the same as the angle of the chamfer. By providing a chamfer of between about 30 and 60 degrees, and most preferably about 45 degrees, the formation of plating slivers at the edges of the surface during lapping can be significantly reduced, and the occurrence of optical device failures resulting from unwanted particles, such as plating slivers, in cavities within the optical devices is also reduced.

Abstract: A method for making a layout for an interconnect layer of a semiconductor device to facilitate uniformity of planarization during manufacture of the semiconductor device includes determining an active interconnect feature density for each of a plurality of layout regions of the interconnect layout. The method further includes adding dummy fill features to each layout region to obtain a desire density of active interconnect features and dummy fill features to facilitate uniformity of planarization during manufacturing of the semiconductor device. By adding dummy fill features to obtain a desired density of active interconnect features and dummy fill features, dummy fill features are not unnecessarily added, and each layout region has a uniform density.

Abstract: A flexible memory overlaying apparatus and method stores repeatedly referenced information, e.g, common global variables, common code segments, interrupt service routines, and/or any other user or system definable information, in spare addressable circuits accessed by a memory aliasing or overlaying module. The memory aliasing module monitors (or snoops) memory access by a processor to redirect access to certain appropriate addressable circuits to provide faster access to the information than would be available in an access made from main memory. The memory overlaying apparatus and method provides an efficient context switching, e.g., during an interrupt, enables a reduction in the size of instruction code requirements, and helps avoid the occurrences of cache misses, and/or thrashing between cached pages.

Abstract: The specification describes a high density IC BGA package in which one or more IC chips are wire bonded to a BGA substrate in a conventional fashion and the BGA substrate is solder ball bonded to a printed wiring board. The standoff between the BGA substrate and the printed wiring board to which it is attached provides a BGA gap which, according to the invention, accommodates one or more IC chips flip-chip bonded to the underside of the BGA substrate. The recognition that state of the art IC chips, especially chips that are thinned, can easily fit into the BGA gap makes practical this efficient use of the BGA gap. The approach of the invention also marries wire bond technology with high packing density flip-chip assembly to produce a low cost, high reliability, state of the art IC package.

Abstract: The present invention provides a method for polishing a semiconductor substrate comprising: (a) polishing a metal layer located on a semiconductor wafer with a slurry at a first polishing rate, wherein the slurry has a predetermined concentration of an oxidizing agent therein; (b) forming a diluted slurry by diluting the polishing slurry with a diluent to substantially reduce the predetermined concentration of the oxidizing agent; and (c) polishing the metal layer at a second polishing rate less than the first polishing rate and in the presence of the diluted slurry.

Abstract: An apparatus for wavelength multiplexing optical signals, wherein the apparatus includes at least one optically conductive sleeve, at least one collimating lens positioned to receive a optical signal from the at least one sleeve, and at least one dichroic splitter positioned to receive the optical signal from the at least one collimating lens. A filter may further be positioned to receive the optical signal from the at least one dichroic splitter in order to further filter the optical signal. The apparatus for wavelength multiplexing is configured to provide optical isolation of at least 75 dB via the combination of the at least one dichroic splitter and filter elements.

Abstract: A semiconductor laser having a single transverse mode operation. Optical power higher than that generated by conventional pump lasers is achieved by widening the gain medium without inducing the second transverse mode. This is accomplished by providing a small refractive index difference between active and blocking regions of the laser. The refractive index difference between the laser active region material and the laser blocking region material at the fundamental frequency is less than about 0.029.

Abstract: The present invention provides methods and apparatus for trimming semiconductor devices and circuits, such as pin electronics circuits used in automated test equipment (ATE) systems and the like, without requiring a laser trimming operation. In a preferred embodiment, the present invention addresses the need to precisely adjust a reference current and/or voltage by replacing a conventional current/voltage reference source with a digital-to-analog (D/A) converter. A select switch or mechanism is preferably coupled to the input of the D/A converter and operatively presents a digital input word to the D/A converter by selectively reading the digital word from at least one of a data register and a fuse register. The data register is preferably used during testing of the overall current or voltage reference by iteratively trying various digital input codes while concurrently measuring the analog output signal from the D/A converter until the output signal sufficiently matches a predetermined output value.

Abstract: A wafer testable integrated circuit (IC) and method for wafer testing the IC. The IC includes outside row buffer areas, inside row buffer areas having bi-directional buffers, routing circuitry between the buffer areas, and IC logic (including internal IC logic directly accessible through at least one inside row buffer area). The internal logic is indirectly accessible through outside row buffer areas via the routing circuitry coupled between the outside row buffer areas and the inside row buffer areas, and the bi-directional buffers of the inside row buffer areas. The method includes supplying a test signal to a first outside row buffer area, routing the test signal from the first outside row buffer area to internal logic accessible through one or more inside row buffer areas, applying the test signal to the internal logic to generate a resultant signal, routing the resultant signal to a second outside row buffer area, and interpreting the resultant signal at the second outside row buffer area.

Abstract: A RAKE receiver for use in a CDMA system is implemented as a transverse correlator in the complex domain. The transverse topology results in the correlator comprising a plurality of serial stages, each stage formed as a canonical unit of a multiplier, adder and memory. When implemented in the complex domain, the multiplier is replaced by multiplexers and the hardware may be significantly reduced by multiplexing between the I and Q components.

Abstract: The specification describes packaging assemblies for micro-electronic machined mechanical systems (MEMS). The MEMS devices in these package assemblies are based on silicon MEMS devices on a silicon support and the MEMS devices and the silicon support are mechanically isolated from foreign materials. Foreign materials pose the potential for differential thermal expansion that deleteriously affects optical alignment in the MEMS devices. In a preferred embodiment the MEMS devices are enclosed in an all-silicon chamber. Mechanical isolation is also aided by using a pin contact array for interconnecting the silicon support substrate for the MEMS devices to the next interconnect level. The use of the pin contact array also allows the MEMS devices to be easily demountable for replacement or repair.

Abstract: The present invention provides a method of manufacturing an interconnect structure within a substrate. The method includes forming an opening in a substrate, which may be a dielectric layer having a low k; for example, one where the dielectric constant ranges from about 3.9 to about 1.9. This method further includes forming a passivation layer within the opening and a photoresist within the opening and over the passivation layer. The passivation layer substantially or completely inhibits the diffusion of elements from the substrate that can deactivate a photo acid generator (PAG) within the photoresist, which prevents the photoresist from developing properly.