Abstract: A system for, and method of, recognizing zero-amplitude symbols in a quadrature amplitude modulated (QAM) signal and a digital receiver incorporating the system or the method. In one embodiment, the system includes: (1) an amplitude detector that extracts a candidate symbol from the signal and locates the candidate symbol relative to a constellation of symbols and (2) a zero-amplitude symbol interpreter, associated with the amplitude detector, that recognizes the candidate symbol as being a zero-amplitude symbol when the candidate symbol is closer to an origin of the constellation than to symbols proximate thereto.

Abstract: The present invention provides a method of depositing a film on a surface of a coil that includes depositing a metal from a target onto a surface of a coil to form a first film on the surface and forming a second film over the first film at a low pressure and at a first power at the target that is substantially higher than a first power at the component's surface. The conditioned deposition tool is well suited for manufacturing integrated circuits.

Abstract: A data storage drive, a method of manufacturing the same, and a drive array that includes multiple such disk storage drives. In one embodiment, the disk storage drive includes: (1) a substrate, (2) a motor located on the substrate, (3) a data storage medium coupled to the motor for movement thereby and (4) a MEMS read arm located on the substrate, having a read head and capable of responding to control signals by moving to cause the read head to traverse portions of the data storage medium thereby to read data therefrom.

Abstract: The present invention provides a method of manufacturing a bipolar transistor. The method may comprise forming a collector in a semiconductor wafer substrate, forming a base in the collector, implanting an oxide region withing said collector and over the base, and forming an emitter over the substrate such that the oxide region is located between the emitter and the base.

Abstract: The present invention provides a method of manufacturing a semiconductor device. In one embodiment, the method includes forming a positive relief structure from a material located on a substrate, the step of forming the positive relief structure leaving an unwanted remnant of said material proximate a base of the positive relief structure. The method further includes cleaning the positive relief structure. In addition, the method includes removing the unwanted remnant with a gas containing fluorine and that is substantially free of hydrogen.

Abstract: A phase-locked loop (PLL), a method of programmably adjusting a phase of a reference clock signal and a synchronous sequential logic circuit incorporating the PLL or the method. In one embodiment, the PLL includes: (1) a digital feedback delay line having a plurality of taps and (2) tap selection logic, coupled to the digital feedback delay line, for activating one of the plurality of taps and thereby insert a corresponding delay into the PLL.

Abstract: A bonded article including a single crystal cathode, for use in projection electron beam lithography, such as the SCALPEL™ system. Because of its single crystalline structure, the single crystal cathode has only slightly misoriented grains. As a result, the single crystal cathode has few structural non-uniformities, and therefore a uniform emission characteristic. The single crystal cathode may be made of at least one of tantalum, tungsten, rhenium, and molybdenum. A local bonding technique for bonding a single crystal cathode with a conventional member. The local bonding technique does not recrystallize a center of the single crystal cathode, and therefore produces a bonded article which is usable in a projection electron lithography system, such as the SCALPEL™ system. The local bonding technique may be laser welding and the single crystal cathode may be made of at least one of tantalum, tungsten, rhenium, and molybdenum.

Abstract: A method of manufacturing an integrated circuit and an integrated circuit employing the same. In one embodiment, the method of manufacturing the integrated circuit includes (1) conformally mapping a micromagnetic device, including a ferromagnetic core, to determine appropriate dimensions therefor, (2) depositing an adhesive over an insulator coupled to a substrate of the integrated circuit and (3) forming the ferromagnetic core of the appropriate dimensions over the adhesive.

Abstract: A frequency and phase estimator simultaneously estimates the frequency and phase of an MPSK modulated signal with a frequency uncertainty range on the order of the symbol rate. The estimator defines a plurality of contiguous bands within the frequency uncertainty range of the signal, estimates the frequency to one of the bands, and utilizes the frequency estimate to derive a phase estimate. In a preferred embodiment, a plurality of signal samples of the frequency shifted signal in each of said bands are accumulated to produce a vector for each band, and the frequency estimate is selected in one of said bands, based upon the magnitude of the corresponding vector. The phase is estimated from the argument of the corresponding vector. The present invention is particularly suited for burst modems or TDMA systems, where frequency and phase estimates must be derived reliably from a limited number of incoming symbols at the beginning of each burst.

Abstract: A layered gate dielectric structure suppresses boron diffusion and provides a gate dielectric structure which is free of trap sites and pinholes, and which does not introduce mobility or drive current problems. The layered gate dielectric structure includes a film which is originally formed as a structurally deficient nitride film which is subsequently converted to either an oxynitride film or a stoichiometric nitride film.

Abstract: An integrated circuit capacitor includes a metal plug in a dielectric layer adjacent a substrate. The metal plug has at least one topographical defect in an uppermost surface portion thereof. A lower metal electrode overlies the dielectric layer and the metal plug. The lower metal electrode includes, in stacked relation, a metal layer, a lower metal nitride layer, an aluminum layer, and an upper metal nitride layer. A capacitor dielectric layer overlies the lower metal electrode, and an upper metal electrode overlies the capacitor dielectric layer. An advantage of this structure is that the stack of metal layers of the lower metal electrode, will prevent undesired defects at the surface of the metal plug from adversely effecting device reliability or manufacturing yield.

Abstract: A process for forming a patterned film structure within a semiconductor device. The process sequentially forms a pattern within a hardmask film and than within a semiconductor or other film formed beneath the hardmask film. The etch bias of both isolated and nested features formed within the films, is substantially the same with respect to a masking film formed over the hardmask film. The process includes a hardmask film etching sequence including an argon treatment step and a hardmask film etching step which is resistant to localized etching effects and includes O2 and C2F6 as etchant gasses.

Abstract: An embedded system for preventing removal of a control circuit pack during programming of a flash memory. The embedded system includes a reset button to be pressed prior to unplugging the control circuit pack and an indicator for signaling when the control circuit pack may be safely removed or unplugged from a shelf. In the case in which the flash memory is uninterruptable, all of the interrupts, except for a power reset interrupt, are inhibited during programming of at least one block of the flash memory. Upon activating the reset button, if programming of the flash memory is completed, then the reset interrupt is invoked and an indicator is enabled thereby signaling that it is safe to remove the control circuit pack. Otherwise, if programming of the flash memory is in progress, then the reset interrupt, like all other interrupts, is inhibited. Alternatively, the flash memory may be interruptable.

Abstract: A method for testing the light emitted by a group of semiconductor light emitting devices arranged to emit light over a testing area, each light emitting device having a p-contact, the method including connecting a plurality of selectively connectable p-contact probes to the p-contacts of respective light emitting devices in the group of light emitting devices, selectively activating one of the light emitting devices in the group of light emitting devices to emit light over the testing area by selectively supplying a predetermined electrical current to the p-contact of the selected light emitting device via its respective p-contact probe, guiding the light emitted by the selected light emitting device via a light funnel having a collection end and a detection end, the collection end being in juxtaposition with all the light emitting devices in the group of light emitting devices, and detecting light exiting the detection end of the light funnel.

Abstract: A thin film resonator (TFR) filter circuit including a plurality of TFRs connected in a series-shunt or shunt-series arrangement between input and output ports of the filter. A method is provided that allows for the shifting of resonant frequency sets in each TFR in respective series arms and shunt legs of the TFR filter circuit, as opposed to a conventional concatenating approach using a plurality of chained-up building blocks of TFRs, where resonant frequency sets in each of the series arms are equal, and where resonant frequency sets in each of the shunt legs are equal. Additionally, each TFR in the filter may have a unique parallel plate electrode capacitance, as opposed to the conventional concatenating approach where all series arm electrodes in the root filter design have equal capacitance, and where all shunt leg electrodes have equal capacitance.

Abstract: A polishing pad formed from closed-cell elastomer foam includes a population of bubbles within the pad. As the pad wears due to polishing and the polishing surface recedes, the freshly formed polishing surface includes pores formed of the newly exposed bubbles. The pores receive and retain polishing slurry and aid in the chemical mechanical polishing process. Pad conditioning is not required because new pores are constantly being created at the pad surface as the surface recedes during polishing. The method for forming the polishing pad includes the injection of gas bubbles into the viscous elastomer material used to form the pad. Process conditions are chosen to maintain gas bubbles within the elastomer material during the curing and solidifying process steps.

Abstract: The present invention provides a method of determining a reliability of a semiconductor device. In an exemplary embodiment, the method determines an oxide stress voltage as a function of an antenna ratio of a semiconductor device, determines an oxide area of the semiconductor device and determines a failure fraction of the semiconductor device as a function of the oxide stress voltage and the oxide area.

Abstract: The element to be simulated is divided into regions, and each region is further divided into a plurality of quadrature nodes. Pairs are formed for all the quadrature nodes. Green's functions are computed and stored for the pairs. Each of the pairs is allocated to either the far field or the near field for purposes of simulation in accordance with a criterion. A Gaussian quadrature is computed for the pairs allocated to the far field while a high order quadrature is computed for those allocated in the near field. The component simulation is arrived after combining information derived from the Gaussian quadrature and the high order quadrature into a matrix which is then solved to obtain the charge distribution. Summation of the charges thus obtained yields the capacitance of the element. The high order quadrature is computed using a plurality of basis functions. The basis functions, denoted &psgr;ik(r′), are 1,x,y,x2,xy,y2. The basis functions are used to compute a set of weights vjk.

Abstract: Operation of CMOS integrated circuits at a reduced voltage are optimized. A digital system comprises a plurality of P-channel metal oxide field effect transistors and a plurality of N-channel metal oxide field effect transistors arranged in complementary symmetry pairs. The P-channel transistors have a PFET conduction threshold voltage. The N-channel transistors have an NFET conduction threshold voltage. The threshold voltages are determined by extrapolation from the (high) gate to source voltage. Each of the N-channel transistors is paired with a corresponding P-channel transistor. The pairing is arranged in complementary symmetry (CMOS). A power supply connected across one of the pair formed from N-channel and P-channel transistors arranged in complementary symmetry is set to a voltage equal to the sum of the PFET conduction threshold voltage and the NFET conduction threshold voltage.

Abstract: A wireless local area network system includes a plurality of base stations connected in a wired local area network. A mobile wireless station can roam through communication cells defined by the base stations. The base stations transmit beacon messages at regular intervals. The mobile station determines the communications quality of the beacon message for the cell in which the mobile station is currently located and if this quality becomes unacceptable, switches to a search mode wherein beacon messages from any base station are received and their communications quality is determined. The mobile station switches to communicate with a base station providing a beacon message with an acceptable communications quality.